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| author | Paolo Bonzini <pbonzini@redhat.com> | 2023-12-22 17:47:38 +0100 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2024-02-28 00:23:39 +0100 |
| commit | d09c79010ffd880dc69e7a21e3cfdef90b928fb8 (patch) | |
| tree | 75932ced011a5659ab23adcef8a5689a8c1f40f0 /docs/devel/writing-monitor-commands.rst | |
| parent | 68fb78d7d5723066ec2cacee7d25d67a4143b42f (diff) | |
| download | focaccia-qemu-d09c79010ffd880dc69e7a21e3cfdef90b928fb8.tar.gz focaccia-qemu-d09c79010ffd880dc69e7a21e3cfdef90b928fb8.zip | |
target/i386: check validity of VMCB addresses
MSR_VM_HSAVE_PA bits 0-11 are reserved, as are the bits above the
maximum physical address width of the processor. Setting them to
1 causes a #GP (see "15.30.4 VM_HSAVE_PA MSR" in the AMD manual).
The same is true of VMCB addresses passed to VMRUN/VMLOAD/VMSAVE,
even though the manual is not clear on that.
Cc: qemu-stable@nongnu.org
Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates", 2022-10-18)
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'docs/devel/writing-monitor-commands.rst')
0 files changed, 0 insertions, 0 deletions