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| author | Richard Henderson <richard.henderson@linaro.org> | 2024-04-25 08:07:45 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2024-04-25 08:07:45 -0700 |
| commit | 83baec642a13a69398a2643a1f905606c13cd363 (patch) | |
| tree | 56ddab1c6d9d1869df33f60f34a934b726ef43ff /docs/devel | |
| parent | 45bef95ca5e9d649e432f2acd82163fb5bccbe47 (diff) | |
| parent | 214652da123e3821657a64691ee556281e9f6238 (diff) | |
| download | focaccia-qemu-83baec642a13a69398a2643a1f905606c13cd363.tar.gz focaccia-qemu-83baec642a13a69398a2643a1f905606c13cd363.zip | |
Merge tag 'pull-target-arm-20240425' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * Implement FEAT_NMI and NMI support in the GICv3 * hw/dma: avoid apparent overflow in soc_dma_set_request * linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code * Add ResetType argument to Resettable hold and exit phase methods * Add RESET_TYPE_SNAPSHOT_LOAD ResetType * Implement STM32L4x5 USART # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmYqMhMZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3uVlD/47U3zYP33y4+wJcRScC0QI # jYd82jS7GhD5YP5QPrIEMaSbDwtYGi4Rez1taaHvZ2fWLg2gE973iixmTaM2mXCd # xPEqMsRXkFrQnC89K5/v9uR04AvHxoM8J2mD2OKnUT0RVBs38WxCUMLETBsD18/q # obs1RzDRhEs5BnwwPMm5HI1iQeVvDRe/39O3w3rZfA8DuqerrNOQWuJd43asHYjO # Gc1QzCGhALlXDoqk11IzjhJ7es8WbJ5XGvrSNe9QLGNJwNsu9oi1Ez+5WK2Eht9r # eRvGNFjH4kQY1YCShZjhWpdzU9KT0+80KLirMJFcI3vUztrYZ027/rMyKLHVOybw # YAqgEUELwoGVzacpaJg73f77uknKoXrfTH25DfoLX0yFCB35JHOPcjU4Uq1z1pfV # I80ZcJBDJ95mXPfyKLrO+0IyVBztLybufedK2aiH16waEGDpgsJv66FB2QRuQBYW # O0i6/4DEUZmfSpOmr8ct+julz7wCWSjbvo6JFWxzzxvD0M5T3AFKXZI244g1SMdh # LS8V7WVCVzVJ5mK8Ujp2fVaIIxiBzlXVZrQftWv5rhyDOiIIeP8pdekmPlI6p5HK # 3/2efzSYNL2UCDZToIq24El/3md/7vHR6DBfBT1/pagxWUstqqLgkJO42jQtTG0E # JY1cZ/EQY7cqXGrww8lhWA== # =WEsU # -----END PGP SIGNATURE----- # gpg: Signature made Thu 25 Apr 2024 03:36:03 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] * tag 'pull-target-arm-20240425' of https://git.linaro.org/people/pmaydell/qemu-arm: (37 commits) tests/qtest: Add tests for the STM32L4x5 USART hw/arm: Add the USART to the stm32l4x5 SoC hw/char/stm32l4x5_usart: Add options for serial parameters setting hw/char/stm32l4x5_usart: Enable serial read and write hw/char: Implement STM32L4x5 USART skeleton reset: Add RESET_TYPE_SNAPSHOT_LOAD docs/devel/reset: Update to new API for hold and exit phase methods hw, target: Add ResetType argument to hold and exit phase methods scripts/coccinelle: New script to add ResetType to hold and exit phases allwinner-i2c, adm1272: Use device_cold_reset() for software-triggered reset hw/misc: Don't special case RESET_TYPE_COLD in npcm7xx_clk, gcr linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code hw/dma: avoid apparent overflow in soc_dma_set_request hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI target/arm: Add FEAT_NMI to max hw/intc/arm_gicv3: Report the VINMI interrupt hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update() hw/intc/arm_gicv3: Implement NMI interrupt priority hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read() hw/intc/arm_gicv3: Add NMI handling CPU interface registers ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'docs/devel')
| -rw-r--r-- | docs/devel/reset.rst | 25 |
1 files changed, 18 insertions, 7 deletions
diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst index 2ea85e7779..9746a4e8a0 100644 --- a/docs/devel/reset.rst +++ b/docs/devel/reset.rst @@ -27,9 +27,7 @@ instantly reset an object, without keeping it in reset state, just call ``resettable_reset()``. These functions take two parameters: a pointer to the object to reset and a reset type. -Several types of reset will be supported. For now only cold reset is defined; -others may be added later. The Resettable interface handles reset types with an -enum: +The Resettable interface handles reset types with an enum ``ResetType``: ``RESET_TYPE_COLD`` Cold reset is supported by every resettable object. In QEMU, it means we reset @@ -37,6 +35,19 @@ enum: from what is a real hardware cold reset. It differs from other resets (like warm or bus resets) which may keep certain parts untouched. +``RESET_TYPE_SNAPSHOT_LOAD`` + This is called for a reset which is being done to put the system into a + clean state prior to loading a snapshot. (This corresponds to a reset + with ``SHUTDOWN_CAUSE_SNAPSHOT_LOAD``.) Almost all devices should treat + this the same as ``RESET_TYPE_COLD``. The main exception is devices which + have some non-deterministic state they want to reinitialize to a different + value on each cold reset, such as RNG seed information, and which they + must not reinitialize on a snapshot-load reset. + +Devices which implement reset methods must treat any unknown ``ResetType`` +as equivalent to ``RESET_TYPE_COLD``; this will reduce the amount of +existing code we need to change if we add more types in future. + Calling ``resettable_reset()`` is equivalent to calling ``resettable_assert_reset()`` then ``resettable_release_reset()``. It is possible to interleave multiple calls to these three functions. There may @@ -150,25 +161,25 @@ in reset. mydev->var = 0; } - static void mydev_reset_hold(Object *obj) + static void mydev_reset_hold(Object *obj, ResetType type) { MyDevClass *myclass = MYDEV_GET_CLASS(obj); MyDevState *mydev = MYDEV(obj); /* call parent class hold phase */ if (myclass->parent_phases.hold) { - myclass->parent_phases.hold(obj); + myclass->parent_phases.hold(obj, type); } /* set an IO */ qemu_set_irq(mydev->irq, 1); } - static void mydev_reset_exit(Object *obj) + static void mydev_reset_exit(Object *obj, ResetType type) { MyDevClass *myclass = MYDEV_GET_CLASS(obj); MyDevState *mydev = MYDEV(obj); /* call parent class exit phase */ if (myclass->parent_phases.exit) { - myclass->parent_phases.exit(obj); + myclass->parent_phases.exit(obj, type); } /* clear an IO */ qemu_set_irq(mydev->irq, 0); |