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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-03-06 11:58:10 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-03-06 11:58:10 +0000 |
| commit | 9b748c5e061b1202fba59afd857e16a693743d90 (patch) | |
| tree | 98d795211d01e15820961febb70af5c87576306d /docs/qemu-cpu-models.texi | |
| parent | b5b6b2b912bbcd3953407da938a8f969577ad3a1 (diff) | |
| parent | 0e081fde8a3d80383adf2e802fc0c03af44c5436 (diff) | |
| download | focaccia-qemu-9b748c5e061b1202fba59afd857e16a693743d90.tar.gz focaccia-qemu-9b748c5e061b1202fba59afd857e16a693743d90.zip | |
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-request' into staging
trivial patches pull request (20190206) - acpi: remove unused functions/variables - tests: remove useless architecture checks - some typo fixes and documentation update - flash_cfi02: fix memory leak # gpg: Signature made Wed 06 Mar 2019 11:05:12 GMT # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-pull-request: thunk: fix of malloc to g_new hostmem-file: simplify ifdef-s in file_backend_memory_alloc() build: Correct explanation of unnest-vars example bswap: Fix accessors syntax in comment doc: fix typos for documents in tree block/pflash_cfi02: Fix memory leak and potential use-after-free hw/acpi: remove unnecessary variable acpi_table_builtin hw/acpi: remove unused function acpi_table_add_builtin() hw/i386/pc.c: remove unused function pc_acpi_init() tests: Remove (mostly) useless architecture checks Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'docs/qemu-cpu-models.texi')
| -rw-r--r-- | docs/qemu-cpu-models.texi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/docs/qemu-cpu-models.texi b/docs/qemu-cpu-models.texi index 475d434d52..1b72584161 100644 --- a/docs/qemu-cpu-models.texi +++ b/docs/qemu-cpu-models.texi @@ -49,7 +49,7 @@ live migration safe. The information that follows provides recommendations for configuring CPU models on x86 hosts. The goals are to maximise performance, while protecting guest OS against various CPU hardware flaws, and optionally -enabling live migration between hosts with hetergeneous CPU models. +enabling live migration between hosts with heterogeneous CPU models. @menu * preferred_cpu_models_intel_x86:: Preferred CPU models for Intel x86 hosts @@ -287,7 +287,7 @@ Must be explicitly turned on for all AMD CPU models. This provides higher performance than virt-ssbd so should be exposed to guests whenever available in the host. virt-ssbd should none the less also be exposed for maximum guest -compatability as some kernels only know about virt-ssbd. +compatibility as some kernels only know about virt-ssbd. @item @code{amd-no-ssb} @@ -296,7 +296,7 @@ Recommended to indicate the host is not vulnerable CVE-2018-3639 Not included by default in any AMD CPU model. -Future hardware genarations of CPU will not be vulnerable to +Future hardware generations of CPU will not be vulnerable to CVE-2018-3639, and thus the guest should be told not to enable its mitigations, by exposing amd-no-ssb. This is mutually exclusive with virt-ssbd and amd-ssbd. @@ -451,7 +451,7 @@ MIPS64 Processor (Release 6, 2014) @item @code{Loongson-2F} -MIPS64 Processor (Longsoon 2, 2008) +MIPS64 Processor (Loongson 2, 2008) @item @code{Loongson-2E} |