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| author | Idan Horowitz <idan.horowitz@gmail.com> | 2022-01-10 18:47:53 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-02-09 08:55:02 +1100 |
| commit | cfc2a2d69d59f02b32df3098ce17e10ab86d43c6 (patch) | |
| tree | 04bfc4cb798c32cdd8572cdfb55c0bea57c3303a /docs/sphinx/kerneldoc.py | |
| parent | 4f152ef27e26d82905244b7cbe344929630d8fae (diff) | |
| download | focaccia-qemu-cfc2a2d69d59f02b32df3098ce17e10ab86d43c6.tar.gz focaccia-qemu-cfc2a2d69d59f02b32df3098ce17e10ab86d43c6.zip | |
accel/tcg: Optimize jump cache flush during tlb range flush
When the length of the range is large enough, clearing the whole cache is faster than iterating over the (possibly extremely large) set of pages contained in the range. This mimics the pre-existing similar optimization done on the flush of the tlb itself. Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com> Message-Id: <20220110164754.1066025-1-idan.horowitz@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'docs/sphinx/kerneldoc.py')
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