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| author | Suraj Jitindar Singh <sjitindarsingh@gmail.com> | 2019-11-28 14:46:57 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-12-17 10:39:48 +1100 |
| commit | f0ec31b1e21718b728753bcbfad54862a587050f (patch) | |
| tree | 86855c0dd678f32de9264905b86246ffc7a38087 /docs/sphinx/kerneldoc.py | |
| parent | 32d0f0d8de37519bcaa720c41f0f693b66016f1b (diff) | |
| download | focaccia-qemu-f0ec31b1e21718b728753bcbfad54862a587050f.tar.gz focaccia-qemu-f0ec31b1e21718b728753bcbfad54862a587050f.zip | |
target/ppc: Add SPR TBU40
The spr TBU40 is used to set the upper 40 bits of the timebase register, present on POWER5+ and later processors. This register can only be written by the hypervisor, and cannot be read. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191128134700.16091-5-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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