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| author | Peter Maydell <peter.maydell@linaro.org> | 2025-02-01 16:39:48 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-02-11 16:22:07 +0000 |
| commit | 07e6b8d7526380a8a30081354f12f48f39d3464e (patch) | |
| tree | 704c82da27a986a94d204cb88fb2dd185219e3ba /docs/system/cpu-models-mips.rst.inc | |
| parent | 6dcd51ccf6815578bd34ea64a33a1eda9cc324e5 (diff) | |
| download | focaccia-qemu-07e6b8d7526380a8a30081354f12f48f39d3464e.tar.gz focaccia-qemu-07e6b8d7526380a8a30081354f12f48f39d3464e.zip | |
target/arm: Handle FPCR.AH in SVE FTMAD
The negation step in the SVE FTMAD insn mustn't negate a NaN when FPCR.AH is set. Pass FPCR.AH to the helper via the SIMD data field, so we can select the correct behaviour. Because the operand is known to be negative, negating the operand is the same as taking the absolute value. Defer this to the muladd operation via flags, so that it happens after NaN detection, which is correct for FPCR.AH. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'docs/system/cpu-models-mips.rst.inc')
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