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authorTomasz Jeznach <tjeznach@rivosinc.com>2025-02-24 16:08:19 -0300
committerAlistair Francis <alistair.francis@wdc.com>2025-03-04 15:42:54 +1000
commit11ecf24c7eda83bb92e24a81425ac6d33a63378e (patch)
tree0026ccff531b244894e865aefccfe549eacdd851 /docs/system/device-url-syntax.rst.inc
parent4faea7e084dc02c6491b55e594ba5d39a75ff38f (diff)
downloadfocaccia-qemu-11ecf24c7eda83bb92e24a81425ac6d33a63378e.tar.gz
focaccia-qemu-11ecf24c7eda83bb92e24a81425ac6d33a63378e.zip
hw/riscv/riscv-iommu: add riscv_iommu_hpm_incr_ctr()
This function will increment a specific counter, generating an interrupt
when an overflow occurs.

Some extra changes in riscv-iommu.c  were required to add this new
helper in riscv-iommu-hpm.c:

- RISCVIOMMUContext was moved to riscv-iommu.h, making it visible in
  riscv-iommu-hpm.c;

- riscv_iommu_notify() is now public.

No behavior change is made since HPM support is not being advertised
yet.

Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250224190826.1858473-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'docs/system/device-url-syntax.rst.inc')
0 files changed, 0 insertions, 0 deletions