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| author | Víctor Colombo <victor.colombo@eldorado.org.br> | 2022-02-09 09:08:56 +0100 |
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| committer | Cédric Le Goater <clg@kaod.org> | 2022-02-09 09:08:56 +0100 |
| commit | 205eb5a89e06f790831b7f6903c92e0dc78b6805 (patch) | |
| tree | 90fbb4127d9a2aea504c8a768549d64c47e95451 /docs/system/i386/amd-memory-encryption.rst | |
| parent | 10895ab6f76beaf2d2b5b450167c5d5102c8c3af (diff) | |
| download | focaccia-qemu-205eb5a89e06f790831b7f6903c92e0dc78b6805.tar.gz focaccia-qemu-205eb5a89e06f790831b7f6903c92e0dc78b6805.zip | |
target/ppc: Change VSX instructions behavior to fill with zeros
ISA v3.1 changed some VSX instructions behavior by changing what the other words/doubleword in the result should contain when the result is only one word/doubleword. e.g. xsmaxdp operates on doubleword 0 and saves the result also in doubleword 0. Before, the second doubleword result was undefined according to the ISA, but now it's stated that it should be zeroed. Even tough the result was undefined before, hardware implementing these instructions already filled these fields with 0s. Changing every ISA version in QEMU to this behavior makes the results match what happens in hardware. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220204181944.65063-1-victor.colombo@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'docs/system/i386/amd-memory-encryption.rst')
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