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authorFabiano Rosas <farosas@linux.ibm.com>2022-02-09 09:08:56 +0100
committerCédric Le Goater <clg@kaod.org>2022-02-09 09:08:56 +0100
commitfce9fbafe910822be093abfbf5fa259d5931aa66 (patch)
treec79b7e2e905895d98fb441d0e37e3836f5384362 /docs/system/i386/amd-memory-encryption.rst
parentc6eaac893af2baef30d3fcce790cbd89fee82a42 (diff)
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target/ppc: Assert if MSR bits differ from msr_mask during exceptions
We currently abort QEMU during the dispatch of an interrupt if we try
to set MSR_HV without having MSR_HVB in the msr_mask. I think we
should verify this for all MSR bits. There is no reason to ever have a
MSR bit set if the corresponding bit is not set in that CPU's
msr_mask.

Note that this is not about the emulated code setting reserved
bits. We clear the new_msr when starting to dispatch an exception, so
if we end up with bits not present in the msr_mask that is a QEMU
programming error.

I kept the HSRR verification for BookS because it is the only CPU
family that has HSRRs.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220207183036.1507882-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'docs/system/i386/amd-memory-encryption.rst')
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