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| author | Stafford Horne <shorne@gmail.com> | 2022-06-24 05:44:56 +0900 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2022-09-04 07:02:57 +0100 |
| commit | 66564c31e4e012c65c84d403c2dc14c0a754047f (patch) | |
| tree | 104bce2af89bda10fbd2c2a0dc802dd124df7032 /docs/system/openrisc | |
| parent | 6a0fc96ad2b16a264ead6b696bdb91a963450dbb (diff) | |
| download | focaccia-qemu-66564c31e4e012c65c84d403c2dc14c0a754047f.tar.gz focaccia-qemu-66564c31e4e012c65c84d403c2dc14c0a754047f.zip | |
target/openrisc: Interrupt handling fixes
When running SMP systems we sometimes were seeing lockups where
IPI interrupts were being raised by never handled.
This looks to be caused by 2 issues in the openrisc interrupt handling
logic.
1. After clearing an interrupt the openrisc_cpu_set_irq handler will
always clear PICSR. This is not correct as masked interrupts
should still be visible in PICSR.
2. After setting PICMR (mask register) and exposed interrupts should
cause an interrupt to be raised. This was not being done so add it.
This patch fixes both issues.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'docs/system/openrisc')
0 files changed, 0 insertions, 0 deletions