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authorRichard Henderson <richard.henderson@linaro.org>2025-09-29 07:25:28 -0700
committerRichard Henderson <richard.henderson@linaro.org>2025-09-29 07:25:28 -0700
commit9b16edec6e9a483469c789475b2065d26b52db35 (patch)
treea54bf2279bbc2a8fc89647c3f64e68b16f69a396 /docs/system
parent4975b64efb5aa4248cbc3760312bbe08d6e71638 (diff)
parent6c51df580d2a64b4e1ef7bdbffeb3615ffe25d43 (diff)
downloadfocaccia-qemu-9b16edec6e9a483469c789475b2065d26b52db35.tar.gz
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Merge tag 'pull-ppc-for-20250928-20250929' of https://gitlab.com/harshpb/qemu into staging
ppc queue for 20250928

* Support for PowerNV11 and PPE42 CPU/Machines.
* Deprecation of Power8E and Power8NVL
* Decodetree patches for some floating-point instructions
* Minor bug fixes, improvements in ppc/spapr/xive/xics.

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# gpg:                 aka "Harsh Prateek Bora <harshpb@linux.ibm.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6B81 0CD6 D2BE 10F3 883D  2142 4544 E994 F9D6 8FBB

* tag 'pull-ppc-for-20250928-20250929' of https://gitlab.com/harshpb/qemu: (27 commits)
  target/ppc: use MAKE_64BIT_MASK for mcrfs exception clear mask
  target/ppc: Deprecate Power8E and Power8NVL
  target/ppc: Introduce macro for deprecating PowerPC CPUs
  target/ppc: Move remaining floating-point move instructions to decodetree.
  target/ppc: Move floating-point move instructions to decodetree.
  target/ppc: Move floating-point compare instructions to decodetree.
  target/ppc: Move floating-point rounding and conversion instructions to decodetree.
  ppc/xive2: Fix integer overflow warning in xive2_redistribute()
  ppc/spapr: init lrdr-capapcity phys with ram size if maxmem not provided
  hw/intc/xics: Add missing call to register vmstate_icp_server
  tests/functional: Add test for IBM PPE42 instructions
  hw/ppc: Add a test machine for the IBM PPE42 CPU
  hw/ppc: Support for an IBM PPE42 CPU decrementer
  target/ppc: Add IBM PPE42 special instructions
  target/ppc: Support for IBM PPE42 MMU
  target/ppc: Add IBM PPE42 exception model
  target/ppc: IBM PPE42 exception flags and regs
  target/ppc: Add IBM PPE42 family of processors
  target/ppc: IBM PPE42 general regs and flags
  tests/powernv: Add PowerNV test for Power11
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'docs/system')
-rw-r--r--docs/system/ppc/powernv.rst9
1 files changed, 5 insertions, 4 deletions
diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst
index f3ec2cc69c..5154794cc8 100644
--- a/docs/system/ppc/powernv.rst
+++ b/docs/system/ppc/powernv.rst
@@ -1,5 +1,5 @@
-PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``)
-==================================================================
+PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``, ``powernv11``)
+================================================================================
 
 PowerNV (as Non-Virtualized) is the "bare metal" platform using the
 OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can
@@ -15,11 +15,12 @@ beyond the scope of what QEMU addresses today.
 Supported devices
 -----------------
 
- * Multi processor support for POWER8, POWER8NVL and POWER9.
+ * Multi processor support for POWER8, POWER8NVL, POWER9, Power10 and Power11.
  * XSCOM, serial communication sideband bus to configure chiplets.
  * Simple LPC Controller.
  * Processor Service Interface (PSI) Controller.
- * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10).
+ * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10 &
+   Power11).
  * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge.
  * Simple OCC is an on-chip micro-controller used for power management tasks.
  * iBT device to handle BMC communication, with the internal BMC simulator