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| author | Inès Varhol <ines.varhol@telecom-paris.fr> | 2024-03-05 22:03:10 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-03-07 12:19:25 +0000 |
| commit | 1cdcfb6e936c25ef470e886ffe86dd46ef36f0f5 (patch) | |
| tree | a76448405d1d91f2171e88a58cdd34984b0806ca /docs | |
| parent | c10a9a517a4518a2b886d5796f90aa1c7a0530f6 (diff) | |
| download | focaccia-qemu-1cdcfb6e936c25ef470e886ffe86dd46ef36f0f5.tar.gz focaccia-qemu-1cdcfb6e936c25ef470e886ffe86dd46ef36f0f5.zip | |
hw/gpio: Implement STM32L4x5 GPIO
Features supported :
- the 8 STM32L4x5 GPIOs are initialized with their reset values
(except IDR, see below)
- input mode : setting a pin in input mode "externally" (using input
irqs) results in an out irq (transmitted to SYSCFG)
- output mode : setting a bit in ODR sets the corresponding out irq
(if this line is configured in output mode)
- pull-up, pull-down
- push-pull, open-drain
Difference with the real GPIOs :
- Alternate Function and Analog mode aren't implemented :
pins in AF/Analog behave like pins in input mode
- floating pins stay at their last value
- register IDR reset values differ from the real one :
values are coherent with the other registers reset values
and the fact that AF/Analog modes aren't implemented
- setting I/O output speed isn't supported
- locking port bits isn't supported
- ADC function isn't supported
- GPIOH has 16 pins instead of 2 pins
- writing to registers LCKR, AFRL, AFRH and ASCR is ineffective
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20240305210444.310665-2-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/system/arm/b-l475e-iot01a.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst index b857a56ca4..0afef8e4f4 100644 --- a/docs/system/arm/b-l475e-iot01a.rst +++ b/docs/system/arm/b-l475e-iot01a.rst @@ -18,6 +18,7 @@ Currently B-L475E-IOT01A machine's only supports the following devices: - STM32L4x5 EXTI (Extended interrupts and events controller) - STM32L4x5 SYSCFG (System configuration controller) - STM32L4x5 RCC (Reset and clock control) +- STM32L4x5 GPIOs (General-purpose I/Os) Missing devices """"""""""""""" @@ -25,7 +26,6 @@ Missing devices The B-L475E-IOT01A does *not* support the following devices: - Serial ports (UART) -- General-purpose I/Os (GPIO) - Analog to Digital Converter (ADC) - SPI controller - Timer controller (TIMER) |