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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-03-24 12:36:38 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-03-24 12:36:39 +0000 |
| commit | a2ecc80db5078dd98b60a7d03af9a4da3e1bad25 (patch) | |
| tree | 7cb9a733899407c431663e8e2e1d5d50cc2f4326 /fpu/softfloat-specialize.h | |
| parent | 2538039f2c26d66053426fb547e4f25e669baf62 (diff) | |
| parent | 0d4c3b8010320a8ebb4061d88510e082b06ed2cc (diff) | |
| download | focaccia-qemu-a2ecc80db5078dd98b60a7d03af9a4da3e1bad25.tar.gz focaccia-qemu-a2ecc80db5078dd98b60a7d03af9a4da3e1bad25.zip | |
Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20160323' into staging
TriCore FPU + bugfixes # gpg: Signature made Wed 23 Mar 2016 08:26:03 GMT using RSA key ID 6B69CA14 # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" * remotes/bkoppelmann/tags/pull-tricore-20160323: target-tricore: Add ftoi and itof instructions target-tricore: Add cmp.f instruction target-tricore: Add div.f instruction target-tricore: Add mul.f instruction target-tricore: add add.f/sub.f instructions target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide target-tricore: Add FPU infrastructure target-tricore: Fix psw_read() clearing too many bits target-tricore: Fix helper_msub64_q_ssov not reseting OVF bit target-tricore: add missing break in insn decode switch stmt Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'fpu/softfloat-specialize.h')
| -rw-r--r-- | fpu/softfloat-specialize.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 0875436b83..a4cbdad452 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -113,7 +113,7 @@ const float16 float16_default_nan = const_float16(0xFE00); #if defined(TARGET_SPARC) const float32 float32_default_nan = const_float32(0x7FFFFFFF); #elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \ - defined(TARGET_XTENSA) || defined(TARGET_S390X) + defined(TARGET_XTENSA) || defined(TARGET_S390X) || defined(TARGET_TRICORE) const float32 float32_default_nan = const_float32(0x7FC00000); #elif SNAN_BIT_IS_ONE const float32 float32_default_nan = const_float32(0x7FBFFFFF); |