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| author | Taylor Simpson <tsimpson@quicinc.com> | 2021-04-08 20:07:38 -0500 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-05-01 08:31:43 -0700 |
| commit | c0336c87b773614eebd23714e3a866bfcd78e9f2 (patch) | |
| tree | 755b6f06f063fe06aa280a17e64f6162f6facfea /fpu | |
| parent | 8c36752435da380ddf2733d499c4be2cdb8c1b6f (diff) | |
| download | focaccia-qemu-c0336c87b773614eebd23714e3a866bfcd78e9f2.tar.gz focaccia-qemu-c0336c87b773614eebd23714e3a866bfcd78e9f2.zip | |
Hexagon (target/hexagon) use softfloat default NaN and tininess
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-11-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'fpu')
| -rw-r--r-- | fpu/softfloat-specialize.c.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index c2f87addb2..9ea318f3e2 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -145,6 +145,9 @@ static FloatParts parts_default_nan(float_status *status) #elif defined(TARGET_HPPA) /* snan_bit_is_one, set msb-1. */ frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); +#elif defined(TARGET_HEXAGON) + sign = 1; + frac = ~0ULL; #else /* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, * S390, SH4, TriCore, and Xtensa. I cannot find documentation |