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| author | Blue Swirl <blauwirbel@gmail.com> | 2012-06-24 07:09:30 +0000 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-06-24 07:09:30 +0000 |
| commit | 99918cec1968b94c8ac3afe51b2a34e5c78c81b3 (patch) | |
| tree | 6c6d23e107bfff988b9c9f442935584322f9ddc9 /hw/arm-misc.h | |
| parent | affe5189907f397514cdd4ee7446595c1246a0e9 (diff) | |
| parent | 5e87975c87b35c66be3f33080c0e5cf6c6d451a5 (diff) | |
| download | focaccia-qemu-99918cec1968b94c8ac3afe51b2a34e5c78c81b3.tar.gz focaccia-qemu-99918cec1968b94c8ac3afe51b2a34e5c78c81b3.zip | |
Merge branch 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
* 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: arm_boot: Conditionalised DTB command line update cadence_ttc: changed master clock frequency cadence_gem: avoid stack-writing buffer-overrun hw/a9mpcore: Fix compilation failure if physaddrs are 64 bit hw/omap.h: Drop broken MEM_VERBOSE tracing hw/armv7m_nvic: Make the NVIC a freestanding class hw/arm_gic: Move CPU interface memory region setup into arm_gic_init hw/arm_gic.c: Make NVIC interrupt numbering a runtime setting hw/arm_gic: Make CPU target registers RAZ/WI on uniprocessor hw/arm_gic: Add qdev property for GIC revision hw/armv7m_nvic: Use MemoryRegions for NVIC specific registers hw/arm_gic: Move NVIC specific reset to armv7m_nvic_reset hw/arm_gic: Remove the special casing of NCPU for the NVIC hw/arm_gic: Remove NVIC ifdefs from gic_state struct arm_boot: Fix typos in comment ARM: Exynos4210 IRQ: Introduce new IRQ gate functionality.
Diffstat (limited to 'hw/arm-misc.h')
| -rw-r--r-- | hw/arm-misc.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/arm-misc.h b/hw/arm-misc.h index 1d51570c88..1f96229d3c 100644 --- a/hw/arm-misc.h +++ b/hw/arm-misc.h @@ -45,9 +45,9 @@ struct arm_boot_info { /* multicore boards that use the default secondary core boot functions * can ignore these two function calls. If the default functions won't * work, then write_secondary_boot() should write a suitable blob of - * code mimicing the secondary CPU startup process used by the board's + * code mimicking the secondary CPU startup process used by the board's * boot loader/boot ROM code, and secondary_cpu_reset_hook() should - * perform any necessary CPU reset handling and set the PC for thei + * perform any necessary CPU reset handling and set the PC for the * secondary CPUs to point at this boot blob. */ void (*write_secondary_boot)(ARMCPU *cpu, |