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authorRichard Henderson <richard.henderson@linaro.org>2022-06-22 07:27:06 -0700
committerRichard Henderson <richard.henderson@linaro.org>2022-06-22 07:27:06 -0700
commit2b049d2c8dc01de750410f8f1a4eac498c04c723 (patch)
treec3bb35def4b1f83c748db2ff21393cf8e1bfa71f /hw/arm/aspeed.c
parentf200ff158d5abcb974a6b597a962b6b2fbea2b06 (diff)
parent92a45bde8cf4257f755ce718fbf7db5f2d607a15 (diff)
downloadfocaccia-qemu-2b049d2c8dc01de750410f8f1a4eac498c04c723.tar.gz
focaccia-qemu-2b049d2c8dc01de750410f8f1a4eac498c04c723.zip
Merge tag 'pull-aspeed-20220622' of https://github.com/legoater/qemu into staging
aspeed queue:

* Extra avocado tests using buildroot images
* Conversion of the I2C model to the registerfield interface
* Support for the I2C new register interface on AST2600
* Various I2C enhancements
* I2C support for the AST1030
* Improvement of the Aspeed SMC and m25p80 qtest

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# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-aspeed-20220622' of https://github.com/legoater/qemu:
  hw: m25p80: fixing individual test failure when tests are running in isolation
  aspeed/hace: Add missing newlines to unimp messages
  aspeed/i2c: Enable SLAVE_ADDR_RX_MATCH always
  hw/i2c/aspeed: add DEV_ADDR in old register mode
  hw/i2c/aspeed: rework raise interrupt trace event
  aspeed: Add I2C buses to AST1030 model
  aspeed/i2c: Add ast1030 controller models
  aspeed: i2c: Move regs and helpers to header file
  aspeed: i2c: Add PKT_DONE IRQ to trace
  aspeed: i2c: Add new mode support
  aspeed: i2c: Use reg array instead of individual vars
  aspeed: i2c: Migrate to registerfields API
  hw/registerfields: Add shared fields macros
  test/avocado/machine_aspeed.py: Add an I2C RTC test
  test/avocado/machine_aspeed.py: Add I2C tests to ast2600-evb
  test/avocado/machine_aspeed.py: Add I2C tests to ast2500-evb
  test/avocado/machine_aspeed.py: Add tests using buildroot images
  test/avocado/machine_aspeed.py: Move OpenBMC tests
  aspeed: Remove fake RTC device on ast2500-evb

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw/arm/aspeed.c')
-rw-r--r--hw/arm/aspeed.c17
1 files changed, 13 insertions, 4 deletions
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 98dc185acd..a06f7c1b62 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -519,10 +519,6 @@ static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
     /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
                      TYPE_TMP105, 0x4d);
-
-    /* The AST2500 EVB does not have an RTC. Let's pretend that one is
-     * plugged on the I2C bus header */
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
 }
 
 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
@@ -1401,6 +1397,18 @@ static void aspeed_minibmc_machine_init(MachineState *machine)
                        AST1030_INTERNAL_FLASH_SIZE);
 }
 
+static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
+{
+    AspeedSoCState *soc = &bmc->soc;
+
+    /* U10 24C08 connects to SDA/SCL Groupt 1 by default */
+    uint8_t *eeprom_buf = g_malloc0(32 * 1024);
+    smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
+
+    /* U11 LM75 connects to SDA/SCL Group 2 by default */
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
+}
+
 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
                                                           void *data)
 {
@@ -1412,6 +1420,7 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
     amc->hw_strap1 = 0;
     amc->hw_strap2 = 0;
     mc->init = aspeed_minibmc_machine_init;
+    amc->i2c_init = ast1030_evb_i2c_init;
     mc->default_ram_size = 0;
     mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
     amc->fmc_model = "sst25vf032b";