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| author | Joel Stanley <joel@jms.id.au> | 2020-05-04 19:07:03 +0930 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-05-11 11:00:26 +0100 |
| commit | 7582591ae745f224a58fd9a36e3b9230fb03bfc2 (patch) | |
| tree | 8bcedef3e9c68535f8961fb3f0b7680e6e27fee9 /hw/arm/aspeed_ast2600.c | |
| parent | 93dd1e6140e2652347cfe7208591d4cd32762d08 (diff) | |
| download | focaccia-qemu-7582591ae745f224a58fd9a36e3b9230fb03bfc2.tar.gz focaccia-qemu-7582591ae745f224a58fd9a36e3b9230fb03bfc2.zip | |
aspeed: Support AST2600A1 silicon revision
There are minimal differences from Qemu's point of view between the A0 and A1 silicon revisions. As the A1 exercises different code paths in u-boot it is desirable to emulate that instead. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 20200504093703.261135-1-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/aspeed_ast2600.c')
| -rw-r--r-- | hw/arm/aspeed_ast2600.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 1a869e09b9..c6e0ab84ac 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -557,9 +557,9 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) dc->realize = aspeed_soc_ast2600_realize; - sc->name = "ast2600-a0"; + sc->name = "ast2600-a1"; sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); - sc->silicon_rev = AST2600_A0_SILICON_REV; + sc->silicon_rev = AST2600_A1_SILICON_REV; sc->sram_size = 0x10000; sc->spis_num = 2; sc->ehcis_num = 2; @@ -571,7 +571,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) } static const TypeInfo aspeed_soc_ast2600_type_info = { - .name = "ast2600-a0", + .name = "ast2600-a1", .parent = TYPE_ASPEED_SOC, .instance_size = sizeof(AspeedSoCState), .instance_init = aspeed_soc_ast2600_init, |