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| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2024-02-15 15:53:30 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2024-02-27 13:47:05 +0100 |
| commit | 944128ee8e26d70a29c66e0e630ceb371750f23c (patch) | |
| tree | e88ec9a4c275e51f640a1d6e4335e8279608ba7c /hw/arm/aspeed_ast2600.c | |
| parent | 1b330dafcdc34315f6837ff3af34dbb4b3106373 (diff) | |
| download | focaccia-qemu-944128ee8e26d70a29c66e0e630ceb371750f23c.tar.gz focaccia-qemu-944128ee8e26d70a29c66e0e630ceb371750f23c.zip | |
aspeed: introduce a new UART0 device name
The Aspeed datasheet refers to the UART controllers
as UART1 - UART13 for the ast10x0, ast2600, ast2500
and ast2400 SoCs and the Aspeed ast2700 introduces an UART0
and the UART controllers as UART0 - UART12.
To keep the naming in the QEMU models
in sync with the datasheet, let's introduce a new UART0 device name
and do the required adjustements.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - Kept original assert() in aspeed_soc_uart_set_chr()
- Fixed 'i' range in connect_serial_hds_to_uarts() loop ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'hw/arm/aspeed_ast2600.c')
| -rw-r--r-- | hw/arm/aspeed_ast2600.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 4ee32ea99d..f74561ecdc 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -666,6 +666,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) sc->wdts_num = 4; sc->macs_num = 4; sc->uarts_num = 13; + sc->uarts_base = ASPEED_DEV_UART1; sc->irqmap = aspeed_soc_ast2600_irqmap; sc->memmap = aspeed_soc_ast2600_memmap; sc->num_cpus = 2; |