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authorPeter Maydell <peter.maydell@linaro.org>2024-10-25 13:35:22 +0100
committerPeter Maydell <peter.maydell@linaro.org>2024-10-25 13:35:22 +0100
commitcea8ac78545a83e1f01c94d89d6f5a3f6b5c05d2 (patch)
tree76d4daac7ae997ed6823539a87e11b89f54417e0 /hw/arm/aspeed_ast27x0.c
parent94be8fd6926cb20c1aa8dd361c6bc10b39b9a376 (diff)
parent1df52a9ac0897687cff7c38705007b2b58065042 (diff)
downloadfocaccia-qemu-cea8ac78545a83e1f01c94d89d6f5a3f6b5c05d2.tar.gz
focaccia-qemu-cea8ac78545a83e1f01c94d89d6f5a3f6b5c05d2.zip
Merge tag 'pull-aspeed-20241024' of https://github.com/legoater/qemu into staging
aspeed queue:

* Fixed GPIO interrupt status when in index mode
* Added GPIO support for the AST2700 SoC and specific test cases
* Fixed crypto controller (HACE) Accumulative hash function
* Converted Aspeed machine avocado tests to the new functional
  framework. SDK tests still to be addressed.
* Fixed issue in the SSI controller when doing writes in user mode
* Added support for the WRSR2 register of Winbond flash devices
* Added SFDP table for the Windbond w25q80bl flash device
* Changed flash device models for the ast1030-a1 EVB

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# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 24 Oct 2024 07:27:14 BST
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full]
# gpg:                 aka "Cédric Le Goater <clg@kaod.org>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-aspeed-20241024' of https://github.com/legoater/qemu:
  test/qtest/aspeed_smc-test: Fix coding style
  hw/arm/aspeed: Correct fmc_model w25q80bl for ast1030-a1 EVB
  hw/arm/aspeed: Correct spi_model w25q256 for ast1030-a1 EVB.
  hw/block/m25p80: Add SFDP table for w25q80bl flash
  hw/block:m25p80: Support write status register 2 command (0x31) for w25q01jvq
  hw/block:m25p80: Fix coding style
  aspeed/smc: Fix write incorrect data into flash in user mode
  tests/functional: Convert most Aspeed machine tests
  hw/misc/aspeed_hace: Fix SG Accumulative hashing
  tests/qtest:ast2700-gpio-test: Add GPIO test case for AST2700
  aspeed/soc: Support GPIO for AST2700
  aspeed/soc: Correct GPIO irq 130 for AST2700
  hw/gpio/aspeed: Add AST2700 support
  hw/gpio/aspeed: Fix clear incorrect interrupt status for GPIO index mode
  hw/gpio/aspeed: Support different memory region ops
  hw/gpio/aspeed: Support to set the different memory size
  hw/gpio/aspeed: Fix coding style

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/aspeed_ast27x0.c')
-rw-r--r--hw/arm/aspeed_ast27x0.c18
1 files changed, 15 insertions, 3 deletions
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 761ee11657..dca660eb6b 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -62,6 +62,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
     [ASPEED_GIC_REDIST]    =  0x12280000,
     [ASPEED_DEV_ADC]       =  0x14C00000,
     [ASPEED_DEV_I2C]       =  0x14C0F000,
+    [ASPEED_DEV_GPIO]      =  0x14C0B000,
 };
 
 #define AST2700_MAX_IRQ 288
@@ -87,8 +88,7 @@ static const int aspeed_soc_ast2700_irqmap[] = {
     [ASPEED_DEV_ADC]       = 130,
     [ASPEED_DEV_XDMA]      = 5,
     [ASPEED_DEV_EMMC]      = 15,
-    [ASPEED_DEV_GPIO]      = 11,
-    [ASPEED_DEV_GPIO_1_8V] = 130,
+    [ASPEED_DEV_GPIO]      = 130,
     [ASPEED_DEV_RTC]       = 13,
     [ASPEED_DEV_TIMER1]    = 16,
     [ASPEED_DEV_TIMER2]    = 17,
@@ -124,7 +124,7 @@ static const int aspeed_soc_ast2700_gic128_intcmap[] = {
 static const int aspeed_soc_ast2700_gic130_intcmap[] = {
     [ASPEED_DEV_I2C]        = 0,
     [ASPEED_DEV_ADC]        = 16,
-    [ASPEED_DEV_GPIO_1_8V]  = 18,
+    [ASPEED_DEV_GPIO]       = 18,
 };
 
 /* GICINT 131 */
@@ -373,6 +373,9 @@ static void aspeed_soc_ast2700_init(Object *obj)
 
     snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
     object_initialize_child(obj, "i2c", &s->i2c, typename);
+
+    snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
+    object_initialize_child(obj, "gpio", &s->gpio, typename);
 }
 
 /*
@@ -658,6 +661,15 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
     }
 
+    /* GPIO */
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
+        return;
+    }
+    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
+                    sc->memmap[ASPEED_DEV_GPIO]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
+                       aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
+
     create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
     create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
     create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);