Merge tag 'pull-target-arm-20250616' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * hw/arm/virt: Check bypass iommu is not set for iommu-map DT property
 * tests/functional: Add a test for the realview-eb-mpcore machine
 * qemu-options.hx: Fix reversed description of icount sleep behavior
 * target/arm: Define raw write for PMU CLR registers
 * docs/interop: convert qed_spec.txt to reStructuredText format
 * hw/arm: make cpu targeted by arm_load_kernel the primary CPU.
 * hw/intc/arm_gic: introduce a first-cpu-index property
 * hw/arm/mps2: Configure the AN500 CPU with 16 MPU regions
 * linux-user/arm: Fix return value of SYS_cacheflush

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# gpg: Signature made Mon 16 Jun 2025 10:05:44 EDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20250616' of https://git.linaro.org/people/pmaydell/qemu-arm:
  linux-user/arm: Fix return value of SYS_cacheflush
  hw/arm/mps2: Configure the AN500 CPU with 16 MPU regions
  hw/intc/arm_gic: introduce a first-cpu-index property
  hw/arm: make cpu targeted by arm_load_kernel the primary CPU.
  docs/interop: convert qed_spec.txt to reStructuredText format
  target/arm: Define raw write for PMU CLR registers
  qemu-options.hx: Fix reversed description of icount sleep behavior
  tests/functional: Add a test for the realview-eb-mpcore machine
  hw/arm/virt: Check bypass iommu is not set for iommu-map DT property

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

1 files changed, 7 insertions, 8 deletions

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 79afb51b8a..3c93d87985 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -744,7 +744,7 @@ static void do_cpu_reset(void *opaque)
             } else {
                 if (arm_feature(env, ARM_FEATURE_EL3) &&
                     (info->secure_boot ||
-                     (info->secure_board_setup && cs == first_cpu))) {
+                     (info->secure_board_setup && cpu == info->primary_cpu))) {
                     /* Start this CPU in Secure SVC */
                     target_el = 3;
                 }
@@ -752,7 +752,7 @@ static void do_cpu_reset(void *opaque)
 
             arm_emulate_firmware_reset(cs, target_el);
 
-            if (cs == first_cpu) {
+            if (cpu == info->primary_cpu) {
                 AddressSpace *as = arm_boot_address_space(cpu, info);
 
                 cpu_set_pc(cs, info->loader_start);
@@ -1239,6 +1239,9 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info)
     info->dtb_filename = ms->dtb;
     info->dtb_limit = 0;
 
+    /* We assume the CPU passed as argument is the primary CPU.  */
+    info->primary_cpu = cpu;
+
     /* Load the kernel.  */
     if (!info->kernel_filename || info->firmware_loaded) {
         arm_setup_firmware_boot(cpu, info);
@@ -1288,12 +1291,8 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info)
 
             object_property_set_int(cpuobj, "psci-conduit", info->psci_conduit,
                                     &error_abort);
-            /*
-             * Secondary CPUs start in PSCI powered-down state. Like the
-             * code in do_cpu_reset(), we assume first_cpu is the primary
-             * CPU.
-             */
-            if (cs != first_cpu) {
+            /* Secondary CPUs start in PSCI powered-down state.  */
+            if (ARM_CPU(cs) != info->primary_cpu) {
                 object_property_set_bool(cpuobj, "start-powered-off", true,
                                          &error_abort);
             }