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| author | Greg Bellows <greg.bellows@linaro.org> | 2015-02-05 13:37:22 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-02-05 13:37:22 +0000 |
| commit | 5097227c15aa89baec1123aac25dd9500a62684d (patch) | |
| tree | a81a3de52a7f32c70c3d38407699b485f8881abc /hw/arm/boot.c | |
| parent | be8e8128595b41b9f609c1507e67d121e65e7173 (diff) | |
| download | focaccia-qemu-5097227c15aa89baec1123aac25dd9500a62684d.tar.gz focaccia-qemu-5097227c15aa89baec1123aac25dd9500a62684d.zip | |
target-arm: Change reset to highest available EL
Update to arm_cpu_reset() to reset into the highest available exception level based on the set ARM features. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1422029835-4696-4-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/boot.c')
| -rw-r--r-- | hw/arm/boot.c | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 52ebd8be9b..a48d1b28d4 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -463,8 +463,26 @@ static void do_cpu_reset(void *opaque) * (SCR.NS = 0), we change that here if non-secure boot has been * requested. */ - if (arm_feature(env, ARM_FEATURE_EL3) && !info->secure_boot) { - env->cp15.scr_el3 |= SCR_NS; + if (arm_feature(env, ARM_FEATURE_EL3)) { + /* AArch64 is defined to come out of reset into EL3 if enabled. + * If we are booting Linux then we need to adjust our EL as + * Linux expects us to be in EL2 or EL1. AArch32 resets into + * SVC, which Linux expects, so no privilege/exception level to + * adjust. + */ + if (env->aarch64) { + if (arm_feature(env, ARM_FEATURE_EL2)) { + env->pstate = PSTATE_MODE_EL2h; + } else { + env->pstate = PSTATE_MODE_EL1h; + } + } + + /* Set to non-secure if not a secure boot */ + if (!info->secure_boot) { + /* Linux expects non-secure state */ + env->cp15.scr_el3 |= SCR_NS; + } } if (CPU(cpu) == first_cpu) { |