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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-02-01 23:06:11 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-01 23:06:26 +0000 |
| commit | b4a8c9ae9758efb6873097f415e9972127ccf418 (patch) | |
| tree | c1d3111448f3847e7f8a5cddfa7bc3ea47d353ef /hw/arm/boot.c | |
| parent | 850bbe1b94445cb84a2f648bc2e8c35ef6188eb4 (diff) | |
| parent | 5b0adce156216fb24dcc5f1683e8b686f3793fff (diff) | |
| download | focaccia-qemu-b4a8c9ae9758efb6873097f415e9972127ccf418.tar.gz focaccia-qemu-b4a8c9ae9758efb6873097f415e9972127ccf418.zip | |
Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20140131' into staging
target-arm queue: * implementation of first part of the A64 Neon instruction set * v8 AArch32 rounding and 16<->64 fp conversion instructions * fix MIDR value on Zynq boards * some minor bugfixes/code cleanups # gpg: Signature made Fri 31 Jan 2014 15:06:34 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * pmaydell/tags/pull-target-arm-20140131: (34 commits) arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes arm_gic: Introduce define for GIC_NR_SGIS target-arm: A64: Add SIMD shift by immediate target-arm: A64: Add simple SIMD 3-same floating point ops target-arm: A64: Add integer ops from SIMD 3-same group target-arm: A64: Add logic ops from SIMD 3 same group target-arm: A64: Add top level decode for SIMD 3-same group target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops target-arm: A64: Add SIMD three-different ABDL instructions target-arm: A64: Add SIMD three-different multiply accumulate insns target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ target-arm: Add set_neon_rmode helper target-arm: Add support for AArch32 SIMD VRINTX target-arm: Add support for AArch32 FP VRINTX target-arm: Add support for AArch32 FP VRINTZ target-arm: Add support for AArch32 FP VRINTR target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM target-arm: Move arm_rmode_to_sf to a shared location. ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/boot.c')
| -rw-r--r-- | hw/arm/boot.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 1c1b0e5258..4036262f50 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -173,6 +173,11 @@ static void default_reset_secondary(ARMCPU *cpu, env->regs[15] = info->smp_loader_start; } +static inline bool have_dtb(const struct arm_boot_info *info) +{ + return info->dtb_filename || info->get_dtb; +} + #define WRITE_WORD(p, value) do { \ stl_phys_notdirty(p, value); \ p += 4; \ @@ -421,7 +426,7 @@ static void do_cpu_reset(void *opaque) env->regs[15] = info->loader_start; } - if (!info->dtb_filename) { + if (!have_dtb(info)) { if (old_param) { set_kernel_args_old(info); } else { @@ -542,7 +547,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) /* for device tree boot, we pass the DTB directly in r2. Otherwise * we point to the kernel args. */ - if (info->dtb_filename || info->get_dtb) { + if (have_dtb(info)) { /* Place the DTB after the initrd in memory. Note that some * kernels will trash anything in the 4K page the initrd * ends in, so make sure the DTB isn't caught up in that. |