diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2019-11-11 13:58:47 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-11-11 13:58:48 +0000 |
| commit | b626eb031a33886a06a153b8715213a2b5816c1c (patch) | |
| tree | 4441671577a639ebb5e96d6d5731e92a739c963b /hw/arm/boot.c | |
| parent | 654efcb511d394c1d3f5292c28503d1d19e5b1d3 (diff) | |
| parent | 45c078f163fd47c35e7505d98928fae63baada7d (diff) | |
| download | focaccia-qemu-b626eb031a33886a06a153b8715213a2b5816c1c.tar.gz focaccia-qemu-b626eb031a33886a06a153b8715213a2b5816c1c.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20191111' into staging
target-arm queue:
* Remove old unassigned_access CPU hook API
* Remove old ptimer_init_with_bh() API
* hw/arm/boot: Set NSACR.{CP11, CP10} in dummy SMC setup routine
# gpg: Signature made Mon 11 Nov 2019 13:56:56 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20191111:
hw/arm/boot: Set NSACR.{CP11, CP10} in dummy SMC setup routine
Remove unassigned_access CPU hook
ptimer: Remove old ptimer_init_with_bh() API
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/boot.c')
| -rw-r--r-- | hw/arm/boot.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/arm/boot.c b/hw/arm/boot.c index ef6724960c..8fb4a63606 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -240,6 +240,9 @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, }; uint32_t board_setup_blob[] = { /* board setup addr */ + 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */ + 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */ + 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */ 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ |