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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-09-20 17:35:36 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-09-20 17:35:36 +0100 |
| commit | d3f5433c7b4aa2d59c6de4175743f4126e181aea (patch) | |
| tree | 4f800d0b63205194e3049a23b378783e21b96d8a /hw/arm/exynos4210.c | |
| parent | c51700273ad9802a21c19f8d2b4bcb67c38e74ac (diff) | |
| parent | e3d038b89f1bf3f09da4d59aa16b16e8305e1a05 (diff) | |
| download | focaccia-qemu-d3f5433c7b4aa2d59c6de4175743f4126e181aea.tar.gz focaccia-qemu-d3f5433c7b4aa2d59c6de4175743f4126e181aea.zip | |
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging
Machine/CPU/NUMA queue, 2017-09-19 # gpg: Signature made Tue 19 Sep 2017 21:17:01 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-next-pull-request: MAINTAINERS: Update git URLs for my trees hw/acpi-build: Fix SRAT memory building in case of node 0 without RAM NUMA: Replace MAX_NODES with nb_numa_nodes in for loop numa: cpu: calculate/set default node-ids after all -numa CLI options are parsed arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly pc: use generic cpu_model parsing vl.c: convert cpu_model to cpu type and set of global properties before machine_init() cpu: make cpu_generic_init() abort QEMU on error qom: cpus: split cpu_generic_init() on feature parsing and cpu creation parts hostmem-file: Add "discard-data" option osdep: Define QEMU_MADV_REMOVE vl: Clean up user-creatable objects when exiting Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/exynos4210.c')
| -rw-r--r-- | hw/arm/exynos4210.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index ee1438a0f4..e8e1d81e62 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -169,15 +169,11 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem) Exynos4210State *s = g_new(Exynos4210State, 1); qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; SysBusDevice *busdev; - ObjectClass *cpu_oc; DeviceState *dev; int i, n; - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9"); - assert(cpu_oc); - for (n = 0; n < EXYNOS4210_NCPUS; n++) { - Object *cpuobj = object_new(object_class_get_name(cpu_oc)); + Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9")); /* By default A9 CPUs have EL3 enabled. This board does not currently * support EL3 so the CPU EL3 property is disabled before realization. |