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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-03-11 13:20:23 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-03-11 13:20:23 +0000 |
| commit | 0ca540dbaea142ec5c3e7a1d12db7139b8317f37 (patch) | |
| tree | 58856f1ab0e13749b2826639ea11fa28341278d1 /hw/arm/pxa2xx.c | |
| parent | ed9b103d3e3102f17791ca53d4a8b17a3de929de (diff) | |
| parent | 72c1d3af6e9c2745edfeaa71918a68bcee4b79db (diff) | |
| download | focaccia-qemu-0ca540dbaea142ec5c3e7a1d12db7139b8317f37.tar.gz focaccia-qemu-0ca540dbaea142ec5c3e7a1d12db7139b8317f37.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140310' into staging
target-arm queue: * implement WFE as yield (improves performance with emulated SMP) * fixes to avoid undefined behaviour shifting left into sign bit * libvixl format string fixes for 32 bit hosts * fix build error when intptr_t and tcg_target_long are different sizes (eg x32) * implement PMCCNTR register * fix incorrect setting of E bit in CPSR (broke booting under KVM on ARM) # gpg: Signature made Mon 10 Mar 2014 15:05:25 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140310: target-arm: Implement WFE as a yield operation hw/arm/musicpal: Avoid shifting left into sign bit hw/ssi/xilinx_spips.c: Avoid shifting left into sign bit hw/arm/omap1.c: Avoid shifting left into sign bit pxa2xx: Don't shift into sign bit libvixl: Fix format strings for several int64_t values target-arm: Fix intptr_t vs tcg_target_long target-arm: Implements the ARM PMCCNTR register target-arm: Fix incorrect setting of E bit in CPSR Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/pxa2xx.c')
| -rw-r--r-- | hw/arm/pxa2xx.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 904277a9da..04291488e4 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -259,7 +259,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, case 1: /* Idle */ - if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */ + if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */ cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); break; } @@ -496,7 +496,7 @@ typedef struct { #define SSCR0_SSE (1 << 7) #define SSCR0_RIM (1 << 22) #define SSCR0_TIM (1 << 23) -#define SSCR0_MOD (1 << 31) +#define SSCR0_MOD (1U << 31) #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) #define SSCR1_RIE (1 << 0) #define SSCR1_TIE (1 << 1) @@ -1006,7 +1006,7 @@ static void pxa2xx_rtc_write(void *opaque, hwaddr addr, switch (addr) { case RTTR: - if (!(s->rttr & (1 << 31))) { + if (!(s->rttr & (1U << 31))) { pxa2xx_rtc_hzupdate(s); s->rttr = value; pxa2xx_rtc_alarm_update(s, s->rtsr); |