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| author | Peter Maydell <peter.maydell@linaro.org> | 2023-09-15 19:54:53 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-10-27 11:41:13 +0100 |
| commit | dfff1000fef24f6686e0be5e6472613985a363dc (patch) | |
| tree | 9fd94af197b25523fb6d52db395f3c669840a2b1 /hw/arm/sbsa-ref.c | |
| parent | 3bcc53980b05dbcdc9bc70fc7ec3bc37320edcbd (diff) | |
| download | focaccia-qemu-dfff1000fef24f6686e0be5e6472613985a363dc.tar.gz focaccia-qemu-dfff1000fef24f6686e0be5e6472613985a363dc.zip | |
target/arm: Implement Neoverse N2 CPU model
Implement a model of the Neoverse N2 CPU. This is an Armv9.0-A processor very similar to the Cortex-A710. The differences are: * no FEAT_EVT * FEAT_DGH (data gathering hint) * FEAT_NV (not yet implemented in QEMU) * Statistical Profiling Extension (not implemented in QEMU) * 48 bit physical address range, not 40 * CTR_EL0.DIC = 1 (no explicit icache cleaning needed) * PMCR_EL0.N = 6 (always 6 PMU counters, not 20) Because it has 48-bit physical address support, we can use this CPU in the sbsa-ref board as well as the virt board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230915185453.1871167-3-peter.maydell@linaro.org
Diffstat (limited to 'hw/arm/sbsa-ref.c')
| -rw-r--r-- | hw/arm/sbsa-ref.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index e8a82618f0..bce44690e5 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -149,6 +149,7 @@ static const char * const valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("neoverse-v1"), + ARM_CPU_TYPE_NAME("neoverse-n2"), ARM_CPU_TYPE_NAME("max"), }; |