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| author | Mostafa Saleh <smostafa@google.com> | 2024-07-15 08:45:13 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-07-18 13:49:30 +0100 |
| commit | eb41313c4be1d9b3c8fcd43ee706c10eabd5c188 (patch) | |
| tree | 6c436595544f4061b5e3f5c22d9f75d251093272 /hw/arm/smmuv3.c | |
| parent | 1ea8a6f59b8d6dbcc5d0aa59380ae45a18231b88 (diff) | |
| download | focaccia-qemu-eb41313c4be1d9b3c8fcd43ee706c10eabd5c188.tar.gz focaccia-qemu-eb41313c4be1d9b3c8fcd43ee706c10eabd5c188.zip | |
hw/arm/smmu: Introduce smmu_iotlb_inv_asid_vmid
Soon, Instead of doing TLB invalidation by ASID only, VMID will be also required. Add smmu_iotlb_inv_asid_vmid() which invalidates by both ASID and VMID. However, at the moment this function is only used in SMMU_CMD_TLBI_NH_ASID which is a stage-1 command, so passing VMID = -1 keeps the original behaviour. Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Mostafa Saleh <smostafa@google.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20240715084519.1189624-14-smostafa@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/smmuv3.c')
| -rw-r--r-- | hw/arm/smmuv3.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index ebf29f3adf..847fc56676 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1357,7 +1357,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) trace_smmuv3_cmdq_tlbi_nh_asid(asid); smmu_inv_notifiers_all(&s->smmu_state); - smmu_iotlb_inv_asid(bs, asid); + smmu_iotlb_inv_asid_vmid(bs, asid, -1); break; } case SMMU_CMD_TLBI_NH_ALL: |