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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-09-01 17:45:38 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-09-01 17:45:38 +0100 |
| commit | 079b1252e9de384385c9da910262312ec2e574c8 (patch) | |
| tree | b18dfec9ce1edd5412bac5bc612f0c2989eacb01 /hw/arm/stm32vldiscovery.c | |
| parent | 4c41a1c595e1ce3fe29f3b7bb22ff7402be9c77d (diff) | |
| parent | 683754c7b61f9e2ff098720ec80c9ab86c54663d (diff) | |
| download | focaccia-qemu-079b1252e9de384385c9da910262312ec2e574c8.tar.gz focaccia-qemu-079b1252e9de384385c9da910262312ec2e574c8.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210901' into staging
* Refactor M-profile systick to use Clocks instead of system_clock_scale global * clock: Provide builtin multiplier/divider * Add A64FX processor model * Enable MVE emulation in Cortex-M55 * hw: Add compat machines for 6.2 * hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleans * hw/arm/raspi: Remove deprecated raspi2/raspi3 aliases # gpg: Signature made Wed 01 Sep 2021 11:35:57 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210901: (51 commits) arm: Remove system_clock_scale global hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scale hw/arm/stellaris: Split stellaris-gptm into its own file hw/arm/stellaris: Fix code style issues in GPTM code hw/timer/armv7m_systick: Use clock inputs instead of system_clock_scale hw/arm/msf2-soc: Wire up refclk hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property hw/arm/msf2_soc: Don't allocate separate MemoryRegions hw/arm/stellaris: Wire sysclk up to armv7m hw/arm/stellaris: split stellaris_sys_init() hw/arm/nrf51: Wire up sysclk hw/arm/stm32vldiscovery: Delete trailing blank line hw/arm/stm32f405: Wire up sysclk and refclk hw/arm/stm32f205: Wire up sysclk and refclk hw/arm/stm32f100: Wire up sysclk and refclk hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize clock: Provide builtin multiplier/divider hw/arm/mps2.c: Connect up armv7m clocks armsse: Wire up systick cpuclk clock hw/arm/armv7m: Create input clocks ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/stm32vldiscovery.c')
| -rw-r--r-- | hw/arm/stm32vldiscovery.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index 7e8191ebf5..04036da3ee 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -27,6 +27,7 @@ #include "qapi/error.h" #include "hw/boards.h" #include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" #include "qemu/error-report.h" #include "hw/arm/stm32f100_soc.h" #include "hw/arm/boot.h" @@ -39,16 +40,15 @@ static void stm32vldiscovery_init(MachineState *machine) { DeviceState *dev; + Clock *sysclk; - /* - * TODO: ideally we would model the SoC RCC and let it handle - * system_clock_scale, including its ability to define different - * possible SYSCLK sources. - */ - system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; + /* This clock doesn't need migration because it is fixed-frequency */ + sysclk = clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(sysclk, SYSCLK_FRQ); dev = qdev_new(TYPE_STM32F100_SOC); qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); + qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); armv7m_load_kernel(ARM_CPU(first_cpu), @@ -63,4 +63,3 @@ static void stm32vldiscovery_machine_init(MachineClass *mc) } DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init) - |