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| author | Eric Auger <eric.auger@redhat.com> | 2025-02-18 19:25:33 +0100 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2025-02-21 07:21:25 -0500 |
| commit | e39e3f8b8dea856f141e9945167d2b18021ef445 (patch) | |
| tree | 1dd8fbcc6067c4e9f404146d82c14af2ca9e54ad /hw/arm/trace-events | |
| parent | 2aaf48bcf27d8b3da5b30af6c1ced464d3df30f7 (diff) | |
| download | focaccia-qemu-e39e3f8b8dea856f141e9945167d2b18021ef445.tar.gz focaccia-qemu-e39e3f8b8dea856f141e9945167d2b18021ef445.zip | |
hw/arm/smmuv3: Move reset to exit phase
Currently the iommu may be reset before the devices it protects. For example this happens with virtio-scsi-pci. when system_reset is issued from qmp monitor: spurious "virtio: zero sized buffers are not allowed" warnings can be observed. This happens because outstanding DMA requests are still happening while the SMMU gets reset. This can also happen with VFIO devices. In that case spurious DMA translation faults can be observed on host. Make sure the SMMU is reset in the 'exit' phase after all DMA capable devices have been reset during the 'enter' or 'hold' phase. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Message-Id: <20250218182737.76722-4-eric.auger@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/arm/trace-events')
| -rw-r--r-- | hw/arm/trace-events | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/arm/trace-events b/hw/arm/trace-events index c64ad344bd..7790db780e 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -56,6 +56,7 @@ smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s" smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t iova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=%s asid=%d vmid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" stage=%d" +smmu_reset_exit(void) "" # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity, int data_bits, int stop_bits) "%s speed=%d parity=%c data=%d stop=%d" |