diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2017-09-04 17:21:24 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-09-04 17:21:24 +0100 |
| commit | 2b483739791b33c46e6084b51edcf62107058ae1 (patch) | |
| tree | fab8d4164ff9c0a73fdaad41ee06815d6163e504 /hw/arm/vexpress.c | |
| parent | 98bfaac788be0ca63d7d010c8d4ba100ff1d8278 (diff) | |
| parent | 7229ec5825df6b933f150b54a8a2bedd2de1864c (diff) | |
| download | focaccia-qemu-2b483739791b33c46e6084b51edcf62107058ae1.tar.gz focaccia-qemu-2b483739791b33c46e6084b51edcf62107058ae1.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170904-2' into staging
target-arm: * collection of M profile cleanups and minor bugfixes * loader: handle ELF files with overlapping zero-init data * virt: allow PMU instantiation with userspace irqchip * wdt_aspeed: Add support for the reset width register * cpu: Define new cpu_transaction_failed() hook * Mark some SoC devices as not user-creatable * arm: Fix aa64 ldp register writeback * arm_gicv3_kvm: Fix compile warning # gpg: Signature made Mon 04 Sep 2017 17:20:40 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20170904-2: (33 commits) arm_gicv3_kvm: Fix compile warning target/arm: Fix aa64 ldp register writeback hw/arm/digic: Mark device with user_creatable = false hw/arm/aspeed_soc: Mark devices as user_creatable = false target/arm: Allow deliver_fault() caller to specify EA bit target/arm: Factor out fault delivery code cputlb: Support generating CPU exceptions on memory transaction failures cpu: Define new cpu_transaction_failed() hook memory.h: Move MemTxResult type to memattrs.h aspeed_soc: Propagate silicon-rev to watchdog watchdog: wdt_aspeed: Add support for the reset width register target/arm/kvm: pmu: improve error handling hw/arm/virt: allow pmu instantiation with userspace irqchip target/arm/kvm: pmu: split init and set-irq stages hw/arm/virt: add pmu interrupt state hw/arm: use defined type name instead of hard-coded string loader: Ignore zero-sized ELF segments loader: Handle ELF files with overlapping zero-initialized data nvic: Implement "user accesses BusFault" SCS region behaviour armv7m_nvic.h: Move from include/hw/arm to include/hw/intc ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/vexpress.c')
| -rw-r--r-- | hw/arm/vexpress.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 528c65ddb6..571dd3609a 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -40,6 +40,8 @@ #include "qemu/error-report.h" #include <libfdt.h> #include "hw/char/pl011.h" +#include "hw/cpu/a9mpcore.h" +#include "hw/cpu/a15mpcore.h" #define VEXPRESS_BOARD_ID 0x8e0 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) @@ -293,7 +295,7 @@ static void a9_daughterboard_init(const VexpressMachineState *vms, memory_region_add_subregion(sysmem, 0x60000000, ram); /* 0x1e000000 A9MPCore (SCU) private memory region */ - init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic, vms->secure); + init_cpus(cpu_model, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure); /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ @@ -378,7 +380,7 @@ static void a15_daughterboard_init(const VexpressMachineState *vms, memory_region_add_subregion(sysmem, 0x80000000, ram); /* 0x2c000000 A15MPCore private memory region (GIC) */ - init_cpus(cpu_model, "a15mpcore_priv", 0x2c000000, pic, vms->secure); + init_cpus(cpu_model, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure); /* A15 daughterboard peripherals: */ |