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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-06-09 17:04:13 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-06-09 17:04:13 +0100 |
| commit | 7721a3044234c46cd6f5f899e7467dc9351f3c8d (patch) | |
| tree | 82162c617563aee0f9d9ca1d9bf2073733975538 /hw/arm/vexpress.c | |
| parent | 14ac57339288c07b47e7e91fa192735158aa6a1e (diff) | |
| parent | 3b1a41381254f6080b5cfeb149c28a9237d42a0b (diff) | |
| download | focaccia-qemu-7721a3044234c46cd6f5f899e7467dc9351f3c8d.tar.gz focaccia-qemu-7721a3044234c46cd6f5f899e7467dc9351f3c8d.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140609-1' into staging
---------------------------------------------------------------- target-arm queue: * support -bios option in vexpress boards * register the Cortex-A57 impdef system registers * fix handling of UXN bit in ARMv8 page tables * complete support of crypto insns in A32/T32 * implement CRC and crypto insns in A64 * fix bugs in generic timer control register ---------------------------------------------------------------- # gpg: Signature made Mon 09 Jun 2014 16:08:26 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140609-1: target-arm: Delete unused iwmmxt_msadb helper target-arm: Fix errors in writes to generic timer control registers target-arm: A64: Implement two-register SHA instructions target-arm: A64: Implement 3-register SHA instructions target-arm: A64: Implement AES instructions target-arm: A32/T32: Mask CRC value in calling code, not helper target-arm: A64: Implement CRC instructions target-arm: VFPv4 implies half-precision extension target-arm: Clean up handling of ARMv8 optional feature bits target-arm: Remove unnecessary setting of feature bits target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64 target-arm: A64: Use PMULL feature bit for PMULL target-arm: add support for v8 VMULL.P64 instruction target-arm: Allow 3reg_wide undefreq to encode more bad size options target-arm: add support for v8 SHA1 and SHA256 instructions target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables target-arm: Prepare cpreg writefns/readfns for EL3/SecExt target-arm/cpu64.c: Actually register Cortex-A57 impdef registers vexpress: Add support for the -bios flag to provide firmware Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/vexpress.c')
| -rw-r--r-- | hw/arm/vexpress.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 33ff422542..f311595d67 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -28,6 +28,7 @@ #include "net/net.h" #include "sysemu/sysemu.h" #include "hw/boards.h" +#include "hw/loader.h" #include "exec/address-spaces.h" #include "sysemu/blockdev.h" #include "hw/block/flash.h" @@ -528,6 +529,18 @@ static void vexpress_common_init(VEDBoardInfo *daughterboard, daughterboard->init(daughterboard, machine->ram_size, machine->cpu_model, pic); + /* + * If a bios file was provided, attempt to map it into memory + */ + if (bios_name) { + const char *fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + if (!fn || load_image_targphys(fn, map[VE_NORFLASH0], + VEXPRESS_FLASH_SIZE) < 0) { + error_report("Could not load ROM image '%s'", bios_name); + exit(1); + } + } + /* Motherboard peripherals: the wiring is the same but the * addresses vary between the legacy and A-Series memory maps. */ |