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| author | Tommy Wu <tommy.wu@sifive.com> | 2023-08-15 23:16:43 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-09-11 11:45:55 +1000 |
| commit | 4df282335b3b13db30123fbcca050e4bf690a9d9 (patch) | |
| tree | 0e38d7ca62ac3201bddafe55b953ae15b9f66204 /hw/arm/virt.c | |
| parent | 4e3adce1244e1ca30ec05874c3eca14911dc0825 (diff) | |
| download | focaccia-qemu-4df282335b3b13db30123fbcca050e4bf690a9d9.tar.gz focaccia-qemu-4df282335b3b13db30123fbcca050e4bf690a9d9.zip | |
target/riscv: Align the AIA model to v1.0 ratified spec
According to the new spec, when vsiselect has a reserved value, attempts from M-mode or HS-mode to access vsireg, or from VS-mode to access sireg, should preferably raise an illegal instruction exception. Signed-off-by: Tommy Wu <tommy.wu@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-ID: <20230816061647.600672-1-tommy.wu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/arm/virt.c')
0 files changed, 0 insertions, 0 deletions