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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-09-23 13:34:11 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-09-29 17:31:52 +0100 |
| commit | 80d2b43b2ff367f38ae4c9616b1ed261ecf801b6 (patch) | |
| tree | 2a1ca500b89092a79c288983958c4a8ea4dc6c09 /hw/arm/virt.c | |
| parent | 7f4fbfb5dc08fe3fb6829bde8e4072d6cb214931 (diff) | |
| download | focaccia-qemu-80d2b43b2ff367f38ae4c9616b1ed261ecf801b6.tar.gz focaccia-qemu-80d2b43b2ff367f38ae4c9616b1ed261ecf801b6.zip | |
target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
In commit 01765386a88868 we fixed a bug where we weren't correctly bracketing changes to some registers with pmu_op_start() and pmu_op_finish() calls for changes which affect whether the PMU counters might be enabled. However, we missed the case of writes to the AArch64 MDCR_EL3 register, because (unlike its AArch32 counterpart) they are currently done directly to the CPU state struct without going through the sdcr_write() function. Give MDCR_EL3 a writefn which handles the PMU start/finish calls. The SDCR writefn then simplfies to "call the MDCR_EL3 writefn after masking off the bits which don't exist in the AArch32 register". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220923123412.1214041-3-peter.maydell@linaro.org
Diffstat (limited to 'hw/arm/virt.c')
0 files changed, 0 insertions, 0 deletions