Merge tag 'pull-target-arm-20220930' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Fix breakage of icount mode when guest touches MDCR_EL3, MDCR_EL2,
   PMCNTENSET_EL0 or PMCNTENCLR_EL0
 * Make writes to MDCR_EL3 use PMU start/finish calls
 * Let AArch32 write to SDCR.SCCD
 * Rearrange cpu64.c so all the CPU initfns are together
 * hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
 * hw/arm/virt: fix some minor issues with generated device tree
 * Fix regression where EL3 could not write to SP_EL1 if there is no EL2

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# gpg: Signature made Fri 30 Sep 2022 09:33:58 EDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20220930' of https://git.linaro.org/people/pmaydell/qemu-arm:
  target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP
  hw/arm/virt: Fix devicetree warning about the SMMU node
  hw/arm/virt: Use "msi-map" devicetree property for PCI
  hw/arm/virt: Fix devicetree warning about the GIC node
  hw/arm/virt: Fix devicetree warning about the root node
  hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
  target/arm: Rearrange cpu64.c so all the CPU initfns are together
  target/arm: Update SDCR_VALID_MASK to include SCCD
  target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
  target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

1 files changed, 4 insertions, 4 deletions

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 0961e053e5..cda9defe8f 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -253,6 +253,7 @@ static void create_fdt(VirtMachineState *vms)
     qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
+    qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
 
     /* /chosen must exist for load_dtb to fill in necessary properties later */
     qemu_fdt_add_subnode(fdt, "/chosen");
@@ -487,6 +488,7 @@ static void fdt_add_its_gic_node(VirtMachineState *vms)
     qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
                             "arm,gic-v3-its");
     qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
+    qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
                                  2, vms->memmap[VIRT_GIC_ITS].base,
                                  2, vms->memmap[VIRT_GIC_ITS].size);
@@ -1359,8 +1361,6 @@ static void create_smmu(const VirtMachineState *vms,
     qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
                      sizeof(irq_names));
 
-    qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle);
-    qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk");
     qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
 
     qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
@@ -1488,8 +1488,8 @@ static void create_pcie(VirtMachineState *vms)
     qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
 
     if (vms->msi_phandle) {
-        qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent",
-                               vms->msi_phandle);
+        qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
+                               0, vms->msi_phandle, 0, 0x10000);
     }
 
     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",