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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-09-20 17:35:36 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-09-20 17:35:36 +0100 |
| commit | d3f5433c7b4aa2d59c6de4175743f4126e181aea (patch) | |
| tree | 4f800d0b63205194e3049a23b378783e21b96d8a /hw/arm/xilinx_zynq.c | |
| parent | c51700273ad9802a21c19f8d2b4bcb67c38e74ac (diff) | |
| parent | e3d038b89f1bf3f09da4d59aa16b16e8305e1a05 (diff) | |
| download | focaccia-qemu-d3f5433c7b4aa2d59c6de4175743f4126e181aea.tar.gz focaccia-qemu-d3f5433c7b4aa2d59c6de4175743f4126e181aea.zip | |
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging
Machine/CPU/NUMA queue, 2017-09-19 # gpg: Signature made Tue 19 Sep 2017 21:17:01 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-next-pull-request: MAINTAINERS: Update git URLs for my trees hw/acpi-build: Fix SRAT memory building in case of node 0 without RAM NUMA: Replace MAX_NODES with nb_numa_nodes in for loop numa: cpu: calculate/set default node-ids after all -numa CLI options are parsed arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly pc: use generic cpu_model parsing vl.c: convert cpu_model to cpu type and set of global properties before machine_init() cpu: make cpu_generic_init() abort QEMU on error qom: cpus: split cpu_generic_init() on feature parsing and cpu creation parts hostmem-file: Add "discard-data" option osdep: Define QEMU_MADV_REMOVE vl: Clean up user-creatable objects when exiting Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/xilinx_zynq.c')
| -rw-r--r-- | hw/arm/xilinx_zynq.c | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 3759cf8dc3..1836a4ed45 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -158,11 +158,9 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, static void zynq_init(MachineState *machine) { ram_addr_t ram_size = machine->ram_size; - const char *cpu_model = machine->cpu_model; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; - ObjectClass *cpu_oc; ARMCPU *cpu; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ext_ram = g_new(MemoryRegion, 1); @@ -174,12 +172,7 @@ static void zynq_init(MachineState *machine) qemu_irq pic[64]; int n; - if (!cpu_model) { - cpu_model = "cortex-a9"; - } - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); - - cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc))); + cpu = ARM_CPU(object_new(machine->cpu_type)); /* By default A9 CPUs have EL3 enabled. This board does not * currently support EL3 so the CPU EL3 property is disabled before @@ -327,6 +320,7 @@ static void zynq_machine_init(MachineClass *mc) mc->max_cpus = 1; mc->no_sdcard = 1; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); } DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) |