diff options
| author | Luc Michel <luc.michel@amd.com> | 2025-09-26 09:07:20 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-10-07 10:35:36 +0100 |
| commit | d82be8c5de7a8bc1602b89678e69312c1716bd10 (patch) | |
| tree | 014b66ea9692f6f5d0f5e9ec970179f4bb36ff1c /hw/arm/xlnx-versal-virt.c | |
| parent | 3471ae96b10bc0a1efeeeff85aea7a823cb57f77 (diff) | |
| download | focaccia-qemu-d82be8c5de7a8bc1602b89678e69312c1716bd10.tar.gz focaccia-qemu-d82be8c5de7a8bc1602b89678e69312c1716bd10.zip | |
hw/arm/xlnx-versal: prepare for FDT creation
The following commits will move FDT creation logic from the xlnx-versal-virt machine to the xlnx-versal SoC itself. Prepare this by passing the FDT handle to the SoC before it is realized. For now the SoC only creates the two clock nodes. The ones from the xlnx-versal virt machine are renamed with a `old-' prefix and will be removed once they are not referenced anymore. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-3-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/xlnx-versal-virt.c')
| -rw-r--r-- | hw/arm/xlnx-versal-virt.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index adadbb7290..d1c65afa2a 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -2,6 +2,7 @@ * Xilinx Versal Virtual board. * * Copyright (c) 2018 Xilinx Inc. + * Copyright (c) 2025 Advanced Micro Devices, Inc. * Written by Edgar E. Iglesias * * This program is free software; you can redistribute it and/or modify @@ -697,10 +698,12 @@ static void versal_virt_init(MachineState *machine) &error_abort); object_property_set_link(OBJECT(&s->soc), "canbus1", OBJECT(s->canbus[1]), &error_abort); - sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); fdt_create(s); + versal_set_fdt(&s->soc, s->fdt); + sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); create_virtio_regions(s); + fdt_add_gem_nodes(s); fdt_add_uart_nodes(s); fdt_add_canfd_nodes(s); @@ -714,8 +717,8 @@ static void versal_virt_init(MachineState *machine) fdt_add_efuse_ctrl_node(s); fdt_add_efuse_cache_node(s); fdt_add_cpu_nodes(s, psci_conduit); - fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz); - fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz); + fdt_add_clk_node(s, "/old-clk125", 125000000, s->phandle.clk_125Mhz); + fdt_add_clk_node(s, "/old-clk25", 25000000, s->phandle.clk_25Mhz); /* Make the APU cpu address space visible to virtio and other * modules unaware of multiple address-spaces. */ |