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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-03-18 13:24:41 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-03-18 13:24:41 +0000 |
| commit | a09863610aefe17390612b7d78d3fba20e43b53e (patch) | |
| tree | dcf39f4859c516dc5447ad3d0f1dc8f72af03ae3 /hw/arm | |
| parent | 1d60bb4b14601e38ed17384277aa4c30c57925d3 (diff) | |
| parent | 79d54c9eac04c554e3c081589542f801ace71797 (diff) | |
| download | focaccia-qemu-a09863610aefe17390612b7d78d3fba20e43b53e.tar.gz focaccia-qemu-a09863610aefe17390612b7d78d3fba20e43b53e.zip | |
Merge tag 'pull-target-arm-20220318' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * Fix sve2 ldnt1 and stnt1 * Fix pauth_check_trap vs SEL2 * Fix handling of LPAE block descriptors * hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size * hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init() * nsis installer: List emulators in alphabetical order * nsis installer: Suppress "ANSI targets are deprecated" warning * nsis installer: Fix mouse-over descriptions for emulators * hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset * Improve M-profile vector table access logging * Xilinx ZynqMP: model CRF and APU control * Fix compile issues on modern Solaris # gpg: Signature made Fri 18 Mar 2022 13:18:20 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20220318' of https://git.linaro.org/people/pmaydell/qemu-arm: (21 commits) util/osdep: Remove some early cruft hw/i386/acpi-build: Avoid 'sun' identifier util/osdep: Avoid madvise proto on modern Solaris hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control hw/misc: Add a model of the Xilinx ZynqMP APU Control hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF hw/misc: Add a model of the Xilinx ZynqMP CRF target/arm: Make rvbar settable after realize hw/arm/xlnx-zynqmp: Add an unimplemented SERDES area target/arm: Log fault address for M-profile faults target/arm: Log M-profile vector table accesses hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset hw/intc: Rename CONFIG_ARM_GIC_TCG into CONFIG_ARM_GICV3_TCG nsis installer: Fix mouse-over descriptions for emulators nsis installer: Suppress "ANSI targets are deprecated" warning nsis installer: List emulators in alphabetical order hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init() hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size target/arm: Fix handling of LPAE block descriptors target/arm: Fix pauth_check_trap vs SEL2 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm')
| -rw-r--r-- | hw/arm/virt.c | 7 | ||||
| -rw-r--r-- | hw/arm/xlnx-zynqmp.c | 46 |
2 files changed, 50 insertions, 3 deletions
diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 46a42502bc..d2e5ecd234 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1852,7 +1852,12 @@ static void finalize_gic_version(VirtMachineState *vms) vms->gic_version = VIRT_GIC_VERSION_2; break; case VIRT_GIC_VERSION_MAX: - vms->gic_version = VIRT_GIC_VERSION_3; + if (module_object_class_by_name("arm-gicv3")) { + /* CONFIG_ARM_GICV3_TCG was set */ + vms->gic_version = VIRT_GIC_VERSION_3; + } else { + vms->gic_version = VIRT_GIC_VERSION_2; + } break; case VIRT_GIC_VERSION_HOST: error_report("gic-version=host requires KVM"); diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 6d0e4116db..5bfe285a19 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -52,6 +52,13 @@ #define QSPI_DMA_ADDR 0xff0f0800 #define NUM_QSPI_IRQ_LINES 2 +#define CRF_ADDR 0xfd1a0000 +#define CRF_IRQ 120 + +/* Serializer/Deserializer. */ +#define SERDES_ADDR 0xfd400000 +#define SERDES_SIZE 0x20000 + #define DP_ADDR 0xfd4a0000 #define DP_IRQ 113 @@ -59,7 +66,7 @@ #define DPDMA_IRQ 116 #define APU_ADDR 0xfd5c0000 -#define APU_SIZE 0x100 +#define APU_IRQ 153 #define IPI_ADDR 0xFF300000 #define IPI_IRQ 64 @@ -276,6 +283,39 @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic) sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]); } +static void xlnx_zynqmp_create_apu_ctrl(XlnxZynqMPState *s, qemu_irq *gic) +{ + SysBusDevice *sbd; + int i; + + object_initialize_child(OBJECT(s), "apu-ctrl", &s->apu_ctrl, + TYPE_XLNX_ZYNQMP_APU_CTRL); + sbd = SYS_BUS_DEVICE(&s->apu_ctrl); + + for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { + g_autofree gchar *name = g_strdup_printf("cpu%d", i); + + object_property_set_link(OBJECT(&s->apu_ctrl), name, + OBJECT(&s->apu_cpu[i]), &error_abort); + } + + sysbus_realize(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, APU_ADDR); + sysbus_connect_irq(sbd, 0, gic[APU_IRQ]); +} + +static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic) +{ + SysBusDevice *sbd; + + object_initialize_child(OBJECT(s), "crf", &s->crf, TYPE_XLNX_ZYNQMP_CRF); + sbd = SYS_BUS_DEVICE(&s->crf); + + sysbus_realize(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, CRF_ADDR); + sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]); +} + static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) { static const struct UnimpInfo { @@ -283,7 +323,7 @@ static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) hwaddr base; hwaddr size; } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = { - { .name = "apu", APU_ADDR, APU_SIZE }, + { .name = "serdes", SERDES_ADDR, SERDES_SIZE }, }; unsigned int nr; @@ -679,6 +719,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) xlnx_zynqmp_create_bbram(s, gic_spi); xlnx_zynqmp_create_efuse(s, gic_spi); + xlnx_zynqmp_create_apu_ctrl(s, gic_spi); + xlnx_zynqmp_create_crf(s, gic_spi); xlnx_zynqmp_create_unimp_mmio(s); for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { |