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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-05-16 22:48:45 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-05-19 18:34:10 +0100 |
| commit | fab8ad39fb75a0d9f097db67b2a334444754e88e (patch) | |
| tree | 28f7f8c3a8d29404c5be34e32e93db3c00f7f265 /hw/arm | |
| parent | 5814d587fe861fe9cab651638959f6db843df54e (diff) | |
| download | focaccia-qemu-fab8ad39fb75a0d9f097db67b2a334444754e88e.tar.gz focaccia-qemu-fab8ad39fb75a0d9f097db67b2a334444754e88e.zip | |
target/arm: Use FIELD definitions for CPACR, CPTR_ELx
We had a few CPTR_* bits defined, but missed quite a few. Complete all of the fields up to ARMv9.2. Use FIELD_EX64 instead of manual extract32. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220517054850.177016-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm')
| -rw-r--r-- | hw/arm/boot.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/arm/boot.c b/hw/arm/boot.c index a47f38dfc9..a8de33fd64 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -761,7 +761,7 @@ static void do_cpu_reset(void *opaque) env->cp15.scr_el3 |= SCR_ATA; } if (cpu_isar_feature(aa64_sve, cpu)) { - env->cp15.cptr_el[3] |= CPTR_EZ; + env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); |