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| author | Anthony Liguori <aliguori@us.ibm.com> | 2012-12-13 11:41:57 -0600 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2012-12-13 11:41:57 -0600 |
| commit | df9330070e671134544f872dc5c027443878b764 (patch) | |
| tree | b1387f5f3f1c86a1ba2efeced0fef37b492844b8 /hw/arm_boot.c | |
| parent | aa1246aee2914424f101a7e462bd1393ececef95 (diff) | |
| parent | 871edc5fdba884929102b89d28ff363c94f0822d (diff) | |
| download | focaccia-qemu-df9330070e671134544f872dc5c027443878b764.tar.gz focaccia-qemu-df9330070e671134544f872dc5c027443878b764.zip | |
Merge remote-tracking branch 'pmaydell/arm-devs.next' into staging
* pmaydell/arm-devs.next: hw/ds1338.c: Fix handling of DAY (wday) register. hw/ds1338.c: Implement support for the control register. hw/ds1338.c: Ensure state is properly initialized. hw/ds1338.c: Fix handling of HOURS register. hw/ds1338.c: Add definitions for various flags in the RTC registers. hw/ds1338.c: Correct bug in conversion to BCD. exynos4210/mct: Avoid infinite loop on non incremental timers hw/arm_gic: fix target CPUs affected by set enable/pending ops xilinx_zynq: Add one variable to avoid overwriting QSPI bus hw/arm_gic_common: Correct GICC_PMR reset value for newer GICs hw/arm_gic: Fix comparison with priority mask register hw/arm_boot, exynos4210, highbank: Fix secondary boot GIC init Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/arm_boot.c')
| -rw-r--r-- | hw/arm_boot.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/hw/arm_boot.c b/hw/arm_boot.c index 92e2cab476..ec3b8d5d12 100644 --- a/hw/arm_boot.c +++ b/hw/arm_boot.c @@ -44,11 +44,17 @@ static uint32_t bootloader[] = { * for an interprocessor interrupt and polling a configurable * location for the kernel secondary CPU entry point. */ +#define DSB_INSN 0xf57ff04f +#define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ + static uint32_t smpboot[] = { - 0xe59f201c, /* ldr r2, gic_cpu_if */ - 0xe59f001c, /* ldr r0, startaddr */ + 0xe59f2028, /* ldr r2, gic_cpu_if */ + 0xe59f0028, /* ldr r0, startaddr */ 0xe3a01001, /* mov r1, #1 */ - 0xe5821000, /* str r1, [r2] */ + 0xe5821000, /* str r1, [r2] - set GICC_CTLR.Enable */ + 0xe3a010ff, /* mov r1, #0xff */ + 0xe5821004, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ + DSB_INSN, /* dsb */ 0xe320f003, /* wfi */ 0xe5901000, /* ldr r1, [r0] */ 0xe1110001, /* tst r1, r1 */ @@ -65,6 +71,11 @@ static void default_write_secondary(ARMCPU *cpu, smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; for (n = 0; n < ARRAY_SIZE(smpboot); n++) { + /* Replace DSB with the pre-v7 DSB if necessary. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V7) && + smpboot[n] == DSB_INSN) { + smpboot[n] = CP15_DSB_INSN; + } smpboot[n] = tswap32(smpboot[n]); } rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), |