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| author | Rob Herring <rob.herring@calxeda.com> | 2011-12-29 06:19:53 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-01-04 13:41:42 +0000 |
| commit | b79f22656f47f0f8b4b89f096f5ae67d0cf268eb (patch) | |
| tree | 60abbc9cd3da493cb701664375c8def16ef9d320 /hw/arm_gic.c | |
| parent | 104a26a236f92cc62b490ea90c3a8dc8f8e07f48 (diff) | |
| download | focaccia-qemu-b79f22656f47f0f8b4b89f096f5ae67d0cf268eb.tar.gz focaccia-qemu-b79f22656f47f0f8b4b89f096f5ae67d0cf268eb.zip | |
arm: add dummy gic security registers
Implement handling for the RAZ/WI gic security registers. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm_gic.c')
| -rw-r--r-- | hw/arm_gic.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 9b521195a5..0339cf59fb 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -282,6 +282,10 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) return ((GIC_NIRQ / 32) - 1) | ((NUM_CPU(s) - 1) << 5); if (offset < 0x08) return 0; + if (offset >= 0x80) { + /* Interrupt Security , RAZ/WI */ + return 0; + } #endif goto bad_reg; } else if (offset < 0x200) { @@ -413,6 +417,8 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis"); } else if (offset < 4) { /* ignored. */ + } else if (offset >= 0x80) { + /* Interrupt Security Registers, RAZ/WI */ } else { goto bad_reg; } |