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authorpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2007-04-07 18:14:41 +0000
committerpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2007-04-07 18:14:41 +0000
commitd537cf6c8624b27ce2b63431d2f8937f6356f652 (patch)
treed7173d79977b4426b2ff225b35c839c8a2e4a215 /hw/arm_pic.h
parentb6e27ab8b12ef6075d85fc505f821643804a3a79 (diff)
downloadfocaccia-qemu-d537cf6c8624b27ce2b63431d2f8937f6356f652.tar.gz
focaccia-qemu-d537cf6c8624b27ce2b63431d2f8937f6356f652.zip
Unify IRQ handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2635 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/arm_pic.h')
-rw-r--r--hw/arm_pic.h6
1 files changed, 1 insertions, 5 deletions
diff --git a/hw/arm_pic.h b/hw/arm_pic.h
index b29914985a..6c5ed1758b 100644
--- a/hw/arm_pic.h
+++ b/hw/arm_pic.h
@@ -14,14 +14,10 @@
 #ifndef ARM_INTERRUPT_H
 #define ARM_INTERRUPT_H 1
 
-/* The first element of an individual PIC state structures should
-   be a pointer to the handler routine.  */
-typedef void (*arm_pic_handler)(void *opaque, int irq, int level);
-
 /* The CPU is also modeled as an interrupt controller.  */
 #define ARM_PIC_CPU_IRQ 0
 #define ARM_PIC_CPU_FIQ 1
-void *arm_pic_init_cpu(CPUState *env);
+qemu_irq *arm_pic_init_cpu(CPUState *env);
 
 #endif /* !ARM_INTERRUPT_H */