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authorPeter Maydell <peter.maydell@linaro.org>2023-06-19 11:20:21 +0100
committerPeter Maydell <peter.maydell@linaro.org>2023-06-19 11:22:18 +0100
commit84693e67fa5a6ffa14133c3038c57988b71dd135 (patch)
tree33ccfac70b436fd68dc3d62da7753e14bcba8af0 /hw/avr/arduino.c
parenta97d3c18f61fd307bffd3579ba35fccd2d88aeb1 (diff)
downloadfocaccia-qemu-84693e67fa5a6ffa14133c3038c57988b71dd135.tar.gz
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target/arm: Convert load/store exclusive and ordered to decodetree
Convert the instructions in the load/store exclusive (STXR,
STLXR, LDXR, LDAXR) and load/store ordered (STLR, STLLR,
LDAR, LDLAR) to decodetree.

Note that for STLR, STLLR, LDAR, LDLAR this fixes an under-decoding
in the legacy decoder where we were not checking that the RES1 bits
in the Rs and Rt2 fields were set.

The new function ldst_iss_sf() is equivalent to the existing
disas_ldst_compute_iss_sf(), but it takes the pre-decoded 'ext' field
rather than taking an undecoded two-bit opc field and extracting
'ext' from it. Once all the loads and stores have been converted
to decodetree disas_ldst_compute_iss_sf() will be unused and
can be deleted.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-9-peter.maydell@linaro.org
Diffstat (limited to 'hw/avr/arduino.c')
0 files changed, 0 insertions, 0 deletions