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| author | Zhao Liu <zhao1.liu@intel.com> | 2024-04-24 23:49:29 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2024-05-22 19:56:27 +0200 |
| commit | 5eb608a13b2dfb772c831d02000a3514d1f137aa (patch) | |
| tree | ba650dfc4c305e3dee236884f37c543a0fd02de6 /hw/char/omap_uart.c | |
| parent | f602eb925ac5d51d09de6c4b32ba8a5142055492 (diff) | |
| download | focaccia-qemu-5eb608a13b2dfb772c831d02000a3514d1f137aa.tar.gz focaccia-qemu-5eb608a13b2dfb772c831d02000a3514d1f137aa.zip | |
i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14]
CPUID[0x8000001D].EAX[bits 25:14] NumSharingCache: number of logical processors sharing cache. The number of logical processors sharing this cache is NumSharingCache + 1. After cache models have topology information, we can use CPUCacheInfo.share_level to decide which topology level to be encoded into CPUID[0x8000001D].EAX[bits 25:14]. Tested-by: Yongwei Ma <yongwei.ma@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Tested-by: Babu Moger <babu.moger@amd.com> Reviewed-by: Babu Moger <babu.moger@amd.com> Message-ID: <20240424154929.1487382-22-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw/char/omap_uart.c')
0 files changed, 0 insertions, 0 deletions