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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-10-22 00:08:46 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-10-29 16:56:12 +1000 |
| commit | 15161e425ee1bb1180f9cec574cda44fb10c0931 (patch) | |
| tree | 9c90b47ae53fcb338a122b1590b6c316e4074410 /hw/core/cpu-common.c | |
| parent | 0e9030376e1a8eb6d15cb5e69dffa09a6ff16b92 (diff) | |
| download | focaccia-qemu-15161e425ee1bb1180f9cec574cda44fb10c0931.tar.gz focaccia-qemu-15161e425ee1bb1180f9cec574cda44fb10c0931.zip | |
target/riscv: change the api for RVF/RVD fmin/fmax
The sNaN propagation behavior has been changed since cd20cee7 in https://github.com/riscv/riscv-isa-manual. In Priv spec v1.10, RVF is v2.0. fmin.s and fmax.s are implemented with IEEE 754-2008 minNum and maxNum operations. In Priv spec v1.11, RVF is v2.2. fmin.s and fmax.s are amended to implement IEEE 754-2019 minimumNumber and maximumNumber operations. Therefore, to prevent the risk of having too many version variables. Instead of introducing an extra *fext_ver* variable, we tie RVF version to Priv version. Though it's not completely accurate but is close enough. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211021160847.2748577-3-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/core/cpu-common.c')
0 files changed, 0 insertions, 0 deletions