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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-07-19 14:01:49 -1000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-10-15 16:39:14 -0700 |
| commit | ef00cd4a22701923583862c48448b43bbcdaca0f (patch) | |
| tree | 4f2940a460284f9fa69ca31448ae1178a4513d9b /hw/core/cpu-common.c | |
| parent | 66345580255f4a9f382cb9e8321a2590025eb1b4 (diff) | |
| download | focaccia-qemu-ef00cd4a22701923583862c48448b43bbcdaca0f.tar.gz focaccia-qemu-ef00cd4a22701923583862c48448b43bbcdaca0f.zip | |
target/mips: Fix single stepping
As per an ancient comment in mips_tr_translate_insn about the expectations of gdb, when restarting the insn in a delay slot we also re-execute the branch. Which means that we are expected to execute two insns in this case. This has been broken since 8b86d6d2580, where we forced max_insns to 1 while single-stepping. This resulted in an exit from the translator loop after the branch but before the delay slot is translated. Increase the max_insns to 2 for this case. In addition, bypass the end-of-page check, for when the branch itself ends the page. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw/core/cpu-common.c')
0 files changed, 0 insertions, 0 deletions