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| author | Babu Moger <babu.moger@amd.com> | 2024-10-24 17:18:24 -0500 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2024-10-31 18:28:32 +0100 |
| commit | 9c07a7af5da66f11a97f56ad1b21f3b12e138a67 (patch) | |
| tree | 33422797225ca6dc5da93b93e67f241b9f75b67b /hw/core/eif.h | |
| parent | 2ec282b8eaaddf5c136f7566b5f61d80288a2065 (diff) | |
| download | focaccia-qemu-9c07a7af5da66f11a97f56ad1b21f3b12e138a67.tar.gz focaccia-qemu-9c07a7af5da66f11a97f56ad1b21f3b12e138a67.zip | |
target/i386: Expose new feature bits in CPUID 8000_0021_EAX/EBX
Newer AMD CPUs support ERAPS (Enhanced Return Address Prediction Security)
feature that enables the auto-clear of RSB entries on a TLB flush, context
switches and VMEXITs. The number of default RSP entries is reflected in
RapSize.
Add the feature bit and feature word to support these features.
CPUID_Fn80000021_EAX
Bits Feature Description
24 ERAPS:
Indicates support for enhanced return address predictor security.
CPUID_Fn80000021_EBX
Bits Feature Description
31-24 Reserved
23:16 RapSize:
Return Address Predictor size. RapSize x 8 is the minimum number
of CALL instructions software needs to execute to flush the RAP.
15-00 MicrocodePatchSize. Read-only.
Reports the size of the Microcode patch in 16-byte multiples.
If 0, the size of the patch is at most 5568 (15C0h) bytes.
Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip
Signed-off-by: Babu Moger <babu.moger@amd.com>
Link: https://lore.kernel.org/r/7c62371fe60af1e9bbd853f5f8e949bf2d908bd0.1729807947.git.babu.moger@amd.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw/core/eif.h')
0 files changed, 0 insertions, 0 deletions