summary refs log tree commit diff stats
path: root/hw/core/generic-loader.c
diff options
context:
space:
mode:
authorGuo Ren <ren_guo@c-sky.com>2022-02-04 10:26:54 +0800
committerAlistair Francis <alistair.francis@wdc.com>2022-02-16 12:25:52 +1000
commit05e6ca5e156d1d114d1eb878cae9744cb4a539e3 (patch)
tree2e4a024c5c68f73b857957c5c3b249afd52e6a6b /hw/core/generic-loader.c
parente8f79343cfc886aaa225cec9faf6881f75945209 (diff)
downloadfocaccia-qemu-05e6ca5e156d1d114d1eb878cae9744cb4a539e3.tar.gz
focaccia-qemu-05e6ca5e156d1d114d1eb878cae9744cb4a539e3.zip
target/riscv: Ignore reserved bits in PTE for RV64
Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
need to ignore them. They cannot be a part of ppn.

1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
   4.4 Sv39: Page-Based 39-bit Virtual-Memory System
   4.5 Sv48: Page-Based 48-bit Virtual-Memory System

2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/core/generic-loader.c')
0 files changed, 0 insertions, 0 deletions