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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-10-09 14:48:39 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-10-12 13:23:14 +0100 |
| commit | 76eff04d166b8fe747adbe82de8b7e060e668ff9 (patch) | |
| tree | ed744634fa6e695f1595ab8beec13568f0af6bfb /hw/core/loader.c | |
| parent | dcf14dfb704519846f396a376339ebdb93eaf049 (diff) | |
| download | focaccia-qemu-76eff04d166b8fe747adbe82de8b7e060e668ff9.tar.gz focaccia-qemu-76eff04d166b8fe747adbe82de8b7e060e668ff9.zip | |
target/arm: Implement SG instruction corner cases
The common situation of the SG instruction is that it is executed from S&NSC memory by a CPU in NS state. That case is handled by v7m_handle_execute_nsc(). However the instruction also has defined behaviour in a couple of other cases: * SG instruction in NS memory (behaves as a NOP) * SG in S memory but CPU already secure (clears IT bits and does nothing else) * SG instruction in v8M without Security Extension (NOP) These can be implemented in translate.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1507556919-24992-10-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'hw/core/loader.c')
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