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| author | Anup Patel <anup.patel@wdc.com> | 2020-03-30 13:57:24 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-04-29 13:16:37 -0700 |
| commit | ee79e7cd47ef47074d7c20c221321c5d31d3683d (patch) | |
| tree | dc13cabf74ec409755af076e92a856ddc26b0141 /hw/core/machine-hmp-cmds.c | |
| parent | 8f67cd6db7375f9133d900b13b300931fbc2e1d8 (diff) | |
| download | focaccia-qemu-ee79e7cd47ef47074d7c20c221321c5d31d3683d.tar.gz focaccia-qemu-ee79e7cd47ef47074d7c20c221321c5d31d3683d.zip | |
riscv: Fix Stage2 SV32 page table walk
As-per RISC-V H-Extension v0.5 draft, the Stage2 SV32 page table has 12bits of VPN[1] and 10bits of VPN[0]. The additional 2bits in VPN[1] is required to handle the 34bit intermediate physical address coming from Stage1 SV32 page table. The 12bits of VPN[1] implies that Stage2 SV32 level-0 page table will be 16KB in size with total 4096 enteries where each entry maps 4MB of memory (same as Stage1 SV32 page table). The get_physical_address() function is broken for Stage2 SV32 level-0 page table because it incorrectly computes output physical address for Stage2 SV32 level-0 page table entry. The root cause of the issue is that get_physical_address() uses the "widened" variable to compute level-0 physical address mapping which changes level-0 mapping size (instead of 4MB). We should use the "widened" variable only for computing index of Stage2 SV32 level-0 page table. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200330082724.120444-1-anup.patel@wdc.com Message-Id: <20200330082724.120444-1-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/core/machine-hmp-cmds.c')
0 files changed, 0 insertions, 0 deletions