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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-06-13 16:17:03 -0700 |
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| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-06-29 10:04:57 -0700 |
| commit | 2b0a39e51e64ae501192b18233bddcc81c098312 (patch) | |
| tree | 12f577bb0f25438bd704eeb97945f6abd5cab60b /hw/core/machine.c | |
| parent | b53357acb4d2c96adaf4dbf1f21999b0e1cf5bda (diff) | |
| download | focaccia-qemu-2b0a39e51e64ae501192b18233bddcc81c098312.tar.gz focaccia-qemu-2b0a39e51e64ae501192b18233bddcc81c098312.zip | |
target/arm: Improve REV32
For the sf version, we are performing two 32-bit bswaps in either half of the register. This is equivalent to performing one 64-bit bswap followed by a rotate. For the non-sf version, we can remove TCG_BSWAP_IZ and the preceding zero-extension. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw/core/machine.c')
0 files changed, 0 insertions, 0 deletions